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FDC655AN Scheda tecnica(PDF) 4 Page - Fairchild Semiconductor |
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FDC655AN Scheda tecnica(HTML) 4 Page - Fairchild Semiconductor |
4 / 4 page FDC655AN Rev.B Figure 10. Single Pulse Maximum Power Dissipation. 0.1 0.5 1 2 5 10 30 50 100 200 500 1000 2000 V , DRAIN TO SOURCE VOLTAGE (V) DS C iss f = 1 MHz V = 0V GS C oss C rss Figure 8. Capacitance Characteristics. Figure 7. Gate Charge Characteristics. Figure 9. Maximum Safe Operating Area. Typical Electrical Characteristics 0.05 0.1 0.2 0.5 1 2 5 10 20 30 50 0.01 0.05 0.1 0.5 1 5 20 50 V , DRAIN-SOURCE VOLTAGE (V) DS RDS(ON) LIMIT V = 10V SINGLE PULSE R =156°C/W T = 25°C GS A θJA DC 1s 10ms 100ms 1ms 100us 0.01 0.1 1 10 100 300 0 1 2 3 4 5 SINGLE PULSE TIME (SEC) SINGLE PULSE R =156 °C/W T = 25°C θJA A 0.00001 0.0001 0.001 0.01 0.1 1 10 100 300 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 t , TIME (sec) 1 Single Pulse D = 0.5 0.1 0.05 0.02 0.01 0.2 Duty Cycle, D = t / t 1 2 R (t) = r(t) * R R = 156 °C/W T - T = P * R (t) A J P(pk) t1 t 2 θJA θJA θJA θJA Figure 11. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in note 1b. Transient thermal response will change depending on the circuit board design. 0 3 6 9 12 15 18 0 2 4 6 8 10 Q , GATE CHARGE (nC) g I = 6.3A D 10V 15V V = 5V DS |
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