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FAN5231 Scheda tecnica(PDF) 4 Page - Fairchild Semiconductor |
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FAN5231 Scheda tecnica(HTML) 4 Page - Fairchild Semiconductor |
4 / 17 page FAN5231 4 REV. 1.1.1 8/15/01 Electrical Specifications (Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3) Parameter Symbol Test Condition Min. Typ. Max Units VCC Supply Nominal Supply Current ICC GATE1, GATE2 Open – 2 2.5 mA Shut-down Supply Current ICCS – 30 50 µA Battery Pin Supply Current IVIN – – 100 µA Battery Pin Leakage Current at Shut-Down IVINSD –– 5 µA Power-On Reset Rising VCC Threshold 4.3 4.5 4.6 V Falling VCC Threshold 3.9 4.1 4.3 V Oscillator Free Running Frequency 255 300 345 kHz Ramp Amplitude, pk-pk Vbat = 16V – 2 – V Ramp Offset – 0.5 – V Reference, DAC and Soft Start VID0-VID4 Input Low Voltage – – 0.8 V VID0-VID4 Input High Voltage 2.0 – – V VID0-VID4 Pull-up Current to VCC – 1 – µA DAC Voltage Accuracy Measured at pin 18 -1.0 – +1.0 % Soft-Start Current During Start-Up ISS VSS = 0V…0.9V 18 27 36 µA Soft-Start Current During Mode Change ISSM VSS = 0.925V…2.0V 350 500 650 µA Enable Enable Voltage Low VENLOW IC Inhibited – – 0.8 V Enable Voltage High VENHIGH IC Enabled Input has internal pull-up current source 2µA typ 2.0 – – V PWM 1 Converter Output Voltage VOUT1 Defined by the current VID code (Table 1) 0.925 – 2.0 V Static Load Regulation 100mA < IVOUT1 < 15.0A -2.0 – +2.0 % Under-Voltage Shut-Down Level VUV1 Percent of the voltage set by VID code. Disabled during dynamic VID code change. 70 75 80 % Under-Voltage Shut Down Delay TDOC1 – 1.4 – µs Over-Voltage VOVP1 Percent of the voltage set by VID code. 110 115 120 % Over-Voltage Shut Down Delay TDOV1 – 2.4 – µs Over-Current Comparator Threshold IOC1 100 135 170 µA PWM 2 Converter Output Voltage VOUT2 1.5 V Load Regulation 100mA < IVOUT3 < 2.1A -2.0 – +2.0 % |
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