Switching Characteristic

at V

From (Input)

R

Symbol

Parameter

To (Output)

C

C

Units

Min

Max

Min

Max

f

MAX

Maximum Clock

25

20

MHz

Frequency

t

PLH

Propagation Delay Time

Clock to

35

39

ns

Low to High Level Output

Ripple Carry

t

PHL

Propagation Delay Time

Clock to

35

44

ns

High to Low Level Output

Ripple Carry

t

PLH

Propagation Delay Time

Clock to

20

24

ns

Low to High Level Output

Any Q

t

PHL

Propagation Delay Time

Clock to

23

32

ns

High to Low Level Output

Any Q

t

PLH

Propagation Delay Time

Enable T to

18

24

ns

Low to High Level Output

Ripple Carry

t

PHL

Propagation Delay Time

Enable T to

18

28

ns

High to Low Level Output

Ripple Carry

t

PLH

Propagation Delay Time

Up/Down to

25

30

ns

Low to High Level Output

Ripple Carry (Note 8)

t

PHL

Propagation Delay Time

Up/Down to

29

38

ns

High to Low Level Output

Ripple Carry (Note 8)

Note 8: The propagation delay from UP/DOWN to RIPPLE CARRY must be measured with the counter at either a minimum or a maximum count. As the logic level

of the up/down input is changed, the ripple carry output will follow. If the count is minimum, the ripple carry output transition will be in phase. If the count is maximum,

the ripple carry output will be out of phase.

3

www.fairchildsemi.com