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DM74AS646WM Scheda tecnica(PDF) 2 Page - Fairchild Semiconductor |
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DM74AS646WM Scheda tecnica(HTML) 2 Page - Fairchild Semiconductor |
2 / 8 page www.fairchildsemi.com 2 Connection Diagram Function Table H—HIGH level; L—LOW level; X—irrelevant; ↑—LOW-to-HIGH level transition Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. Inputs Data I/O (Note 1) Operation or Function G DIR CAB CBA SAB SBA A1 thru A8 B1 thru B8 DM74AS646 DM74AS648 H X H or L H or L X X Input Input Isolation, Hold Storage Isolation, Hold Storage X ↑↑ X X Store A and B Data Store A and B Data L L X X X L Output Input Real Time B Data to A Bus Real Time B Data to A Bus L X H or L X H Stored B Data to A Bus Stored B Data to A Bus L H X X L X Input Output Real Time A Data to B Bus Real Time A Data to B Bus H H or L X H X Stored A Data to B Bus Stored A Data to B Bus XX ↑ X X X Input Unspecified (Note 1) Store A, B Unspecified (Note 1) Store A, B Unspecified (Note 1) XX X ↑ X X Unspecified (Note 1) Input Store B, A Unspecified (Note 1) Store B, A Unspecified (Note 1) |
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