© 2000 Fairchild Semiconductor Corporation

DS006280

www.fairchildsemi.com

April 1984

Revised March 2000

DM74AS32

Quad 2-Input OR Gate

General Description

This device contains four independent gates, each of which

performs the logic OR function.

Features

s Switching specifications at 50 pF

s Switching specifications guaranteed over full

s Advanced oxide-isolated, ion-implanted

Schottky TTL process

s Functionally and pin for pin compatible with Schottky,

low power Schottky, and advanced low power Schottky

TTL counterpart

s Improved AC performance over Schottky, low power

Schottky and advanced low power Schottky counter-

parts

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Y

= A + B

H

= HIGH Logic Level

L

= LOW Logic Level

Order Number

Package Number

Package Description

DM74AS32M

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

DM74AS32SJ

M14D

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

DM74AS32N

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Inputs

Output

AB

Y

LLL

LH

H

HL

H

HHH