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AD7634BSTZ Scheda tecnica(PDF) 6 Page - Analog Devices |
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AD7634BSTZ Scheda tecnica(HTML) 6 Page - Analog Devices |
6 / 32 page AD7634 Data Sheet Rev. B | Page 6 of 32 Parameter Symbol Min Typ Max Unit SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES2 (See Figure 44, Figure 45, and Figure 47) External SDCLK, SCCLK Setup Time t31 5 ns External SDCLK Active Edge to SDOUT Delay t32 2 18 ns SDIN/SCIN Setup Time t33 5 ns SDIN/SCIN Hold Time t34 5 ns External SDCLK/SCCLK Period t35 25 ns External SDCLK/SCCLK High t36 10 ns External SDCLK/SCCLK Low t37 10 ns 1 In warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time. 2 In serial interface modes, the SDSYNC, SDSCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum. 3 In serial master read during convert mode. See Table 4 for serial master read after convert mode. Table 4. Serial Clock Timings in Master Read After Convert Mode DIVSCLK[1] 0 0 1 1 DIVSCLK[0] Symbol 0 1 0 1 Unit SYNC to SDCLK First Edge Delay Minimum t18 3 20 20 20 ns Internal SDCLK Period Minimum t19 30 60 120 240 ns Internal SDCLK Period Maximum t19 45 90 180 360 ns Internal SDCLK High Minimum t20 15 30 60 120 ns Internal SDCLK Low Minimum t21 10 25 55 115 ns SDOUT Valid Setup Time Minimum t22 4 20 20 20 ns SDOUT Valid Hold Time Minimum t23 5 8 35 90 ns SDCLK Last Edge to SYNC Delay Minimum t24 5 7 35 90 ns BUSY High Width Maximum t28 Warp Mode 1.98 2.78 4.34 7.46 μs Normal Mode 2.23 3.03 4.59 7.71 μs Impulse Mode 2.48 3.28 4.84 7.96 μs NOTES 1. IN SERIAL INTERFACE MODES, THE SYNC, SDCLK, AND SDOUT ARE DEFINED WITH A MAXIMUM LOAD CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. 1.6mA IOL 500µA IOH 1.4V TO OUTPUT PIN CL 60pF Figure 2. Load Circuit for Digital Interface Timing, SDOUT, SYNC, and SDCLK Outputs, CL = 10 pF 0.8V 2V 2V 0.8V 0.8V 2V tDELAY tDELAY Figure 3. Voltage Reference Levels for Timing |
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