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CD4099BCN Scheda tecnica(PDF) 1 Page - Fairchild Semiconductor |
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CD4099BCN Scheda tecnica(HTML) 1 Page - Fairchild Semiconductor |
1 / 6 page October 1987 Revised January 1999 © 1999 Fairchild Semiconductor Corporation DS005984.prf www.fairchildsemi.com CD4099BC 8-Bit Addressable Latch General Description The CD4099BC is an 8-bit addressable latch with three address inputs (A0–A2), an active low enable input (E), active high clear input (CL), a data input (D), and eight out- puts (Q0–Q7). Data is entered into a particular bit in the latch when that bit is addressed by the address inputs and the enable (E) is LOW. Data entry is inhibited when enable (E) is HIGH. When clear (CL) and enable (E) are HIGH, all outputs are LOW. When clear (CL) is HIGH and enable (E) is LOW, the channel demultiplexing occurs. The bit that is addressed has an active output which follows the data input while all unaddressed bits are held LOW. When operating in the addressable latch mode (E = CL = LOW), changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode (E = HIGH, CL = LOW). Features s Wide supply voltage range: 3.0V to 15V s High noise immunity: 0.45 VDD (typ.) s Low power TTL: fan out of 2 driving 74L compatibility: or 1 driving 74LS s Serial to parallel capability s Storage register capability s Random (addressable) data entry s Active high demultiplexing capability s Common active high clear Ordering Code: Connection Diagram Pin Assignments for DIP Top View Truth Table Order Number Package Number Package Description CD4099BCN N16E 16-Lead Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Mode Selection E CL Addressed Unaddressed Mode Latch Latch L L Follows Data Holds Previous Data Addressable Latch H L Holds Previous Data Holds Previous Data Memory L H Follows Data Reset to “0” Demultiplexer H H Reset to “0” Reset to “0” Clear |
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