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AD736JNZ Scheda tecnica(PDF) 11 Page - Analog Devices

Il numero della parte AD736JNZ
Spiegazioni elettronici  Low Cost, Low Power, True RMS-to-DC Converter
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

AD736JNZ Scheda tecnica(HTML) 11 Page - Analog Devices

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Data Sheet
AD736
Rev. I | Page 11 of 20
Mathematically, the rms value of a voltage is defined (using a
simplified equation) as
( )2
rms
V
Avg
V
=
This involves squaring the signal, taking the average, and
then obtaining the square root. True rms converters are smart
rectifiers; they provide an accurate rms reading regardless of the
type of waveform being measured. However, average responding
converters can exhibit very high errors when their input signals
deviate from their precalibrated waveform; the magnitude of
the error depends on the type of waveform being measured. For
example, if an average responding converter is calibrated to
measure the rms value of sine wave voltages and then is used to
measure either symmetrical square waves or dc voltages, the
converter has a computational error 11% (of reading) higher
than the true rms value (see Table 5).
CALCULATING SETTLING TIME USING FIGURE 16
Figure 16 can be used to closely approximate the time required
for the AD736 to settle when its input level is reduced in amplitude.
The net time required for the rms converter to settle is the
difference between two times extracted from the graph (the
initial time minus the final settling time). As an example, consider
the following conditions: a 33 µF averaging capacitor, a 100 mV
initial rms input level, and a final (reduced) 1 mV input level.
From Figure 16, the initial settling time (where the 100 mV line
intersects the 33 µF line) is approximately 80 ms.
The settling time corresponding to the new or final input level
of 1 mV is approximately 8 seconds. Therefore, the net time for
the circuit to settle to its new value is 8 seconds minus 80 ms,
which is 7.92 seconds. Note that because of the smooth decay
characteristic inherent with a capacitor/diode combination, this
is the total settling time to the final value (that is, not the settling
time to 1%, 0.1%, and so on, of the final value). In addition, this
graph provides the worst-case settling time because the AD736
settles very quickly with increasing input levels.
RMS MEASUREMENT—CHOOSING THE OPTIMUM
VALUE FOR CAV
Because the external averaging capacitor, CAV, holds the
rectified input signal during rms computation, its value directly
affects the accuracy of the rms measurement, especially at low
frequencies. Furthermore, because the averaging capacitor
appears across a diode in the rms core, the averaging time
constant increases exponentially as the input signal is reduced.
This means that as the input level decreases, errors due to
nonideal averaging decrease, and the time required for the
circuit to settle to the new rms level increases. Therefore, lower
input levels allow the circuit to perform better (due to increased
averaging) but increase the waiting time between measurements.
Obviously, when selecting CAV, a trade-off between computational
accuracy and settling time is required.
Table 5. Error Introduced by an Average Responding Circuit when Measuring Common Waveforms
Waveform Type 1 V Peak Amplitude
Crest Factor
(VPEAK/V rms)
True RMS
Value (V)
Average Responding Circuit
Calibrated to Read RMS Value of
Sine Waves (V)
% of Reading Error Using
Average Responding Circuit
Undistorted Sine Wave
1.414
0.707
0.707
0
Symmetrical Square Wave
1.00
1.00
1.11
+11.0
Undistorted Triangle Wave
1.73
0.577
0.555
−3.8
Gaussian Noise (98% of Peaks <1 V)
3
0.333
0.295
−11.4
Rectangular
2
0.5
0.278
−44
Pulse Train
10
0.1
0.011
−89
SCR Waveforms
50% Duty Cycle
2
0.495
0.354
−28
25% Duty Cycle
4.7
0.212
0.150
−30


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