© 2005 Fairchild Semiconductor Corporation

DS500098

www.fairchildsemi.com

February 1998

Revised June 2005

74VHC161284

IEEE 1284 Transceiver

General Description

The VHC161284 contains eight bidirectional data buffers

and eleven control/status buffers to implement a full

IEEE 1284 compliant interface. The device supports the

IEEE 1284 standard and is intended to be used in

Extended Capabilities Port mode (ECP). The pinout allows

for easy connection from the Peripheral (A-side) to the

Host (cable side).

Outputs on the cable side can be configured to be either

open drain or high drive (

r 14 mA). The pull-up and pull-

down series termination resistance of these outputs on the

cable side is optimized to drive an external cable. In addi-

tion, all inputs (except HLH) and outputs on the cable side

ply to provide proper termination and pull-ups for open

drain mode.

Outputs on the Peripheral side are standard LOW-drive

Features

s Supports IEEE 1284 Level 1 and Level 2 signaling

standards for bidirectional parallel communications

between personal computers and printing peripherals

s Replaces the function of two (2) 74ACT1284 devices

s All inputs have hysteresis to provide noise margin

s B and Y output resistance optimized to drive external

cable

s B and Y outputs in high impedance mode during power

down

s Inputs and outputs on cable side have internal pull-up

resistors

s Flow-through pin configuration allows easy interface

between the Peripheral and Host

Ordering Code:

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

Connection Diagram

Ordering Number Package Number

Package Description

74VHC161284MEA

MS48A

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

74VHC161284MTD

MTD48

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide