© 2001 Fairchild Semiconductor Corporation

DS500173

www.fairchildsemi.com

October 1998

Revised August 2001

74VCX16835

Low Voltage 18-Bit Universal Bus Driver

with 3.6V Tolerant Inputs and Outputs

General Description

The VCX16835 low voltage 18-bit universal bus driver

combines D-type latches and D-type flip-flops to allow data

flow in transparent, latched and clocked modes.

Data flow is controlled by output-enable (OE), latch-enable

(LE), and clock (CLK) inputs. The device operates in

Transparent Mode when LE is held HIGH. The device

operates in clocked mode when LE is LOW and CLK is tog-

Positive Edge Transition of the Clock. When OE is LOW,

the output data is enabled. When OE is HIGH the output

port is in a high impedance state.

The 74VCX16835 is designed for low voltage (1.65V to

The 74VCX16835 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Features

s Compatible with PC100 DIMM module specifications

s 3.6V tolerant inputs and outputs

s Power-down high impedance inputs and outputs

s Supports live insertion/withdrawal (Note 1)

±24mA @ 3.0V

±18mA @ 2.3V

±6mA @ 1.65V

s Latchup performance exceeds 300 mA

s ESD performance:

Human body model

> 2000V

Machine model

>200V

s Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA) (Preliminary)

Note 1: To ensure the high-impedance state during power up or power

the minimum value of the resistor is determined by the current sourcing

capability of the driver.

Ordering Code:

Note 2: BGA package available in Tape and Reel only.

Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Order Number

Package Number

Package Description

74VCX16835GX

(Note 2)

BGA54A

(Preliminary)

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[TAPE and REEL]

74VCX16835MTD

(Note 3)

MTD56

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide