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74LVX125SJ Scheda tecnica(PDF) 1 Page - Fairchild Semiconductor |
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74LVX125SJ Scheda tecnica(HTML) 1 Page - Fairchild Semiconductor |
1 / 6 page © 2005 Fairchild Semiconductor Corporation DS012007 www.fairchildsemi.com February 1994 Revised February 2005 74LVX125 Low Voltage Quad Buffer with 3-STATE Outputs General Description The LVX125 contains four independent non-inverting buff- ers with 3-STATE outputs. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems. Features s Input voltage level translation from 5V to 3V s Ideal for low power/low noise 3.3V applications s Guaranteed simultaneous switching noise level and dynamic threshold performance Ordering Code: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. Logic Symbol IEEE/IEC Pin Descriptions Connection Diagram Truth Table H HIGH Voltage Level L LOW Voltage Level Z High Impedance X Immaterial Order Number Package Package Description Number 74LVX125M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LVX125SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVX125MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74LVX125MTCX_NL (Note 1) MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pin Names Description An Inputs OEn Output Enable Inputs On Outputs Inputs Output OEn An On LLL LH H HX Z |
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