© 2005 Fairchild Semiconductor Corporation

DS012159

www.fairchildsemi.com

October 1996

Revised February 2005

74LVX132

Low Voltage Quad 2-Input NAND Schmitt Trigger

General Description

The LVX132 contains four 2-input NAND Schmitt Trigger

Gates. The pin configuration and function are the same as

the LVX00 but the inputs have hysteresis between the pos-

itive-going and negative-going input thresholds, which are

capable of transforming slowly changing input signals into

sharply defined, jitter-free output signals, thus providing

greater noise margins than conventional gates.

The inputs tolerate voltages up to 7V allowing the interface

of 5V systems to 3V systems.

Features

s Input voltage level translation from 5V to 3V

s Ideal for low power/low noise 3.3V applications

s Guaranteed simultaneous switching noise level and

dynamic threshold performance

Ordering Code:

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Pb-Free package per JEDEC J-STD-020B.

Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.

Logic Diagram

Connection Diagram

Pin Descriptions

Order Number

Package

Package Description

Number

74LVX132M

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74LVX132SJ

M14D

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LVX132MTC

MTC14

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74LVX132MTCX_NL

(Note 1)

MTC14

Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

Pin Names

Descriptions

Inputs

Outputs