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74LVTH16952MTDX Scheda tecnica(PDF) 2 Page - Fairchild Semiconductor |
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74LVTH16952MTDX Scheda tecnica(HTML) 2 Page - Fairchild Semiconductor |
2 / 8 page www.fairchildsemi.com 2 Connection Diagram Pin Descriptions Truth Table (Note 1) H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = Output High Impedance = LOW-to-HIGH Transition. NC = No Change (state established by last valid CP) B0 = State established by last valid CP Note 1: A to B data flow shown; B to A flow control is the same, but used OEBAn, CPBAn and CEBn. Pin Names Description A0–A16 Data Register A Inputs B-Register 3-STATE Outputs B0–B16 Data Register B Inputs A-Register 3-STATE Outputs CPABn, CPBAn Clock Pulse Inputs CEAn, CEBn Clock Enable OEABn, OEBAn Output Enable Inputs Inputs Internal Register Output An CPABn CEAn OEABn Value Bn XX H L NC B0 XX H H NC Z L LL L L L LH L Z H LL H H H LH H Z XL X L NC B0 XH X L NC B0 XL X H NC Z XH X H NC Z |
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