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74LVTH322374GX Scheda tecnica(PDF) 2 Page - Fairchild Semiconductor |
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74LVTH322374GX Scheda tecnica(HTML) 2 Page - Fairchild Semiconductor |
2 / 6 page Preliminary www.fairchildsemi.com 2 Connection Diagram (Top Thru View) Pin Descriptions for FBGA FBGA Pin Assignments Truth Tables H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance Oo = Previous Oo before HIGH-to-LOW of CP Functional Description The LVTH322374 consists of thirty-two edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 32-bit operation. Each byte has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their indi- vidual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operation of the OEn input does not affect the state of the flip-flops. Pin Names Description OEn Output Enable Input (Active LOW) CPn Clock Pulse Input I0–I31 Inputs O0–O31 3-STATE Outputs 123 456 A O1 O0 OE1 CP1 I0 I1 B O3 O2 GND GND I2 I3 C O5 O4 VCC1 VCC1 I4 I5 D O7 O6 GND GND I6 I7 E O9 O8 GND GND I8 I9 F O11 O10 VCC1 VCC1 I10 I11 G O13 O12 GND GND I12 I13 H O14 O15 OE2 CP2 I15 I14 J O17 O16 OE3 CP3 I16 I17 K O19 O18 GND GND I18 I19 L O21 O20 VCC2 VCC2 I20 I21 M O23 O22 GND GND I22 I23 N O25 O24 GND GND I24 I25 P O27 O26 VCC2 VCC2 I26 I27 R O29 O28 GND GND I28 I29 T O30 O31 OE4 CP4 I31 I30 Inputs Outputs Inputs Outputs CP1 OE1 I0–I7 O0–O7 CP2 OE2 I8–I15 O8–O15 LH H LH H LL L LL L LL X Oo LL X Oo XH X Z XHX Z Inputs Outputs Inputs Outputs CP3 OE3 I16–I23 O16–O23 CP4 OE4 I24–I31 O24–O31 LH H LH H LL L LL L LL X Oo LL X Oo XH X Z XHX Z |
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