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74LVTH16652MEA Scheda tecnica(PDF) 4 Page - Fairchild Semiconductor |
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74LVTH16652MEA Scheda tecnica(HTML) 4 Page - Fairchild Semiconductor |
4 / 9 page www.fairchildsemi.com 4 Functional Description In the transceiver mode, data present at the HIGH imped- ance port may be stored in either the A or B register or both. The select (SABn, SBAn) controls can multiplex stored and real-time. The examples below demonstrate the four fundamental bus-management functions that can be performed with the LVTH16652. Data on the A or B data bus, or both can be stored in the internal D flip-flop by LOW-to-HIGH transitions at the appropriate Clock Inputs (CPABn, CPBAn) regardless of the Select or Output Enable Inputs. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D flip-flops by simulta- neously enabling OEABn and OEBAn. In this configuration each Output reinforces its Input. Thus when all other data sources to the two sets of bus lines are in a HIGH imped- ance state, each set of bus lines will remain at its last state. Real-Time Transfer Bus B to Bus A Storage Real-Time Transfer Bus A to Bus B Transfer Storage Data to A or B OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1 LL X X X L OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1 XH XX X LX X XX LH XX OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1 HH X X L X OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1 HL H or L H or L H H |
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