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74LCX241MSA Scheda tecnica(PDF) 1 Page - Fairchild Semiconductor |
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74LCX241MSA Scheda tecnica(HTML) 1 Page - Fairchild Semiconductor |
1 / 10 page © 2005 Fairchild Semiconductor Corporation DS012639 www.fairchildsemi.com August 1998 Revised March 2005 74LCX241 Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs General Description The LCX241 is an octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver. The device is designed for low voltage (2.5V or 3.3V) VCC applications with capa- bility of interfacing to a 5V signal environment. The LCX241 is fabricated with an advanced CMOS tech- nology to achieve high speed operation while maintaining CMOS low power dissipation. Features s 5V tolerant inputs and outputs s 2.3V – 3.6V VCC specifications provided s 6.5 ns tPD max (VCC 3.3V), 10 PA ICC max s Power-down high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s Implements patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance: Human Body Model ! 2000V Machine Model ! 200V Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC and OE should be tied to GND through a resistor: the minimum value or the resistor is determined by the current-sourcing capa- bility of the driver. Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Pin Descriptions Order Number Package Number Package Description 74LCX241WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LCX241SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LCX241MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74LCX241MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pin Names Description OE1, OE2 3-STATE Output Enable Inputs I0–I7 Inputs O0–O7 Outputs |
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