74LCX16543MTD datasheet(2/9 Pages) FAIRCHILD

Il numero della parte	74LCX16543MTD

Spiegazioni elettronici	Low Voltage 16-Bit Registered Transceiver with 5V Tolerant Inputs and Outputs

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Produttore elettronici	FAIRCHILD [Fairchild Semiconductor]

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Pin Descriptions

Data I/O Control Table

H

= HIGH Voltage Level

L

= LOW Voltage Level

X

= Immaterial

A-to-B data flow shown; B-to-A flow control is the same, except using CEBAn, LEBAn and OEBAn

Functional Description

The LCX16543 contains sixteen non-inverting transceivers

with 3-STATE outputs. The device is byte controlled with

each byte functioning identically, but independent of the

other. The control pins may be shorted together to obtain

full 16-bit operation. The following description applies to

each byte. For data flow from A to B, for example, the

A-to-B Enable (CEABn) input must be LOW in order to

enter data from A0–A15 or take data from B0–B15, as indi-

cated in the Data I/O Control Table. With CEABn LOW, a

LOW signal on the A-to-B Latch Enable (LEABn) input

makes the A-to-B latches transparent; a subsequent LOW-

to-HIGH transition of the LEABn signal puts the A latches in

the storage mode and their outputs no longer change with

the A inputs. With CEABn and OEABn both LOW, the

3-STATE B output buffers are active and reflect the data

present at the output of the A latches. Control of data flow

from B to A is similar, but using the CEBAn, LEBAn and

OEBAn inputs.

Pin Names

Description

OEABn

A-to-B Output Enable Input (Active LOW)

OEBAn

B-to-A Output Enable Input (Active LOW)

CEABn

A-to-B Enable Input (Active LOW)

CEBAn

B-to-A Enable Input (Active LOW)

LEABn

A-to-B Latch Enable Input (Active LOW)

LEBAn

B-to-A Latch Enable Input (Active LOW)

A0–A15

A-to-B Data Inputs or B-to-A 3-STATE Outputs

B0–B15

B-to-A Data Inputs or A-to-B 3-STATE Outputs

Inputs

Latch Status

Output Buffers

CEABn

LEABn

OEABn

(Byte n)

H

X

Latched

High Z

X

H

X

Latched

—

L

X

Transparent

—

XX

H

—

High Z

LX

L

—

Driving

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