© 2002 Fairchild Semiconductor Corporation

DS012407

www.fairchildsemi.com

March 1995

Revised June 2002

74LCX16500

Low Voltage 18-Bit Universal Bus Transceivers with

5V Tolerant Inputs and Outputs

General Description

These 18-bit universal bus transceivers combine D-type

latches and D-type flip-flops to allow data flow in transpar-

ent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable

(OEAB and OEBA), latch-enable (LEAB and LEBA), and

clock (CLKAB and CLKBA) inputs.

The LCX16500 is designed for low voltage (2.5V or 3.3V)

signal environment.

The LCX16500 is fabricated with an advanced CMOS tech-

nology to achieve high speed operation while maintaining

CMOS low power.

Features

s 5V tolerant inputs and outputs

s Power down high impedance inputs and outputs

s Supports live insertion/withdrawal (Note 1)

s

±24 mA output drive (V

s Uses patented noise/EMI reduction circuitry

s Latch-up performance exceeds 500 mA

s ESD performance:

Human body model

> 2000V

Machine model

> 200V

s Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA)

Note 1: To ensure the high-impedance state during power up or down, OE

value or the resistor is determined by the current-sourcing capability of the

driver.

Ordering Code:

Note 2: Ordering code “G” indicates Trays.

Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Order Number

Package Number

Package Description

74LCX16500G

(Note 2)(Note 3)

BGA54A

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

74LCX16500MEA

(Note 3)

MS56A

56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

74LCX16500MTD

(Note 3)

MTD56

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide