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74F74SJ Scheda tecnica(PDF) 2 Page - Fairchild Semiconductor |
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74F74SJ Scheda tecnica(HTML) 2 Page - Fairchild Semiconductor |
2 / 7 page www.fairchildsemi.com 2 Unit Loading/Fan Out Truth Table H (h) = HIGH Voltage Level L (l) = LOW Voltage Level X = Immaterial Q0 = Previous Q (Q) before LOW-to-HIGH Clock Transition Lower case letters indicate the state of the referenced input or output one setup time prior to the LOW-to-HIGH clock transition. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL D1, D2 Data Inputs 1.0/1.0 20 µA/−0.6 mA CP1, CP2 Clock Pulse Inputs (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA CD1, CD2 Direct Clear Inputs (Active LOW) 1.0/3.0 20 µA/−1.8 mA SD1, SD2 Direct Set Inputs (Active LOW) 1.0/3.0 20 µA/−1.8 mA Q1, Q1, Q2, Q2 Outputs 50/33.3 −1 mA/20 mA Inputs Outputs SD CD CP D Q Q LH X X H L HL X X L H LL X X H H HH hH L HH lL H HH L X Q0 Q0 |
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