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74F160ASC Scheda tecnica(PDF) 3 Page - Fairchild Semiconductor |
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74F160ASC Scheda tecnica(HTML) 3 Page - Fairchild Semiconductor |
3 / 8 page 3 www.fairchildsemi.com Functional Description The 74F160A and 74F162A count modulo-10 in the BCD (8421) sequence. From state 9 (HLLH) they increment to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs (except due to Master Reset of the (F160A) occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fun- damental modes of operation, in order of precedence: asynchronous reset (F160A), synchronous reset (F162A), parallel load, count-up and hold. Five control inputs—Mas- ter Reset (MR, F160A), Synchronous Reset (SR, F162A), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET)—determine the mode of oper- ation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR (F160A) or SR (F162A) HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting. The F160A and F162A use D-type edge-triggered flip-flops and changing the SR, PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. The Terminal Count (TC) output is HIGH when CET is HIGH and counter is in state 9. To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Please refer to the F568 data sheet. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, counters or registers. In the F160A and F162A decade counters, the TC output is fully decoded and can only be HIGH in state 9. If a decade counter is preset to an illegal state, or assumes an illegal state when power is applied, it will return to the normal sequence within two counts, as shown in the State Diagram. Logic Equations: Count Enable = CEP × CET × PE TC = Q 0 × Q 1× Q 2 × Q3 × CET Mode Select Table *For 74’F162A only H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial State Diagram Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. *SR PE CET CEP Action on the Rising Clock Edge ( ) L X X X Reset (Clear) H L X X Load (Pn → Qn) H H H H Count (Increment) H H L X No Change (Hold) H H X L No Change (Hold) |
Codice articolo simile - 74F160ASC |
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Descrizione simile - 74F160ASC |
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