 |
Motore di ricerca datesheet componenti elettronici |
|
|
Motore di ricerca datesheet componenti elettronici |
|
74ACT715-RSC Scheda tecnica(PDF) 6 Page - Fairchild Semiconductor |
|
||||||||||||||||||||||||||||||
74ACT715-RSC Scheda tecnica(HTML) 6 Page - Fairchild Semiconductor |
|
|
6 / 14 page  www.fairchildsemi.com 6 Addressing Logic The register addressing logic is composed of two blocks of logic. The first is the address register and counter (ADDRCNTR), and the second is the address decode (ADDRDEC). ADDRCNTR LOGIC Addresses for the data registers can be generated by one of two methods. Manual addressing requires that each byte of each register that needs to be loaded needs to be addressed. To load both bytes of all 19 registers would require a total of 57 load cycles (19 address and 38 data cycles). Auto Addressing requires that only the initial regis- ter value be specified. The Auto Load sequence would require only 39 load cycles to completely program all regis- ters (1 address and 38 data cycles). In the auto load sequence the low order byte of the data register will be written first followed by the high order byte on the next load cycle. At the time the High Byte is written the address counter is incremented by 1. The counter has been imple- mented to loop on the initial value loaded into the address register. For example: If a value of 0 was written into the address register then the counter would count from 0 to 18 before resetting back to 0. If a value of 15 was written into the address register then the counter would count from 15 to 18 before looping back to 15. If a value greater than or equal to 18 is placed into the address register the counter will continuously loop on this value. Auto addressing is initi- ated on the falling edge of LOAD when ADDRDATA is 0 and LHBYTE is 1. Incrementing and loading of data regis- ters will not commence until the falling edge of LOAD after ADDRDATA goes to 1. The next rising edge of LOAD will load the first byte of data. Auto Incrementing is disabled on the falling edge of LOAD after ADDRDATA and LHBYTE goes low. Manual Addressing Mode Auto Addressing Mode Cycle # Load Falling Edge Load Rising Edge 1 Enable Manual Addressing Load Address m 2 Enable Lbyte Data Load Load Lbyte m 3 Enable Hbyte Data Load Load Hbyte m 4 Enable Manual Addressing Load Address n 5 Enable Lbyte Data Load Load Lbyte n 6 Enable Hbyte Data Load Load Hbyte n Cycle # Load Falling Edge Load Rising Edge 1 Enable Auto Addressing Load Start Address n 2 Enable Lbyte Data Load Load Lbyte (n) 3 Enable Hbyte Data Load Load Hbyte (n); Inc Counter 4 Enable Lbyte Data Load Load Lbyte (n +1) 5 Enable Hbyte Data Load Load Hbyte (n +1); Inc Counter 6 Enable Manual Addressing Load Address |
Codice articolo simile - 74ACT715-RSC |
|
Descrizione simile - 74ACT715-RSC |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEETIT.COM |
| Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Italian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
