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74ACT109 Scheda tecnica(PDF) 5 Page - Fairchild Semiconductor

Il numero della parte 74ACT109
Spiegazioni elettronici  Dual JK Positive Edge-Triggered Flip-Flop
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Produttore elettronici  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

74ACT109 Scheda tecnica(HTML) 5 Page - Fairchild Semiconductor

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AC Operating Requirements for AC
Note 8: Voltage Range 3.3 is 3.3V
± 0.3V
Voltage Range 5.0 is 5.0V
± 0.5V
AC Electrical Characteristics for ACT
Note 9: Voltage Range 5.0 is 5.0V
± 0.5V
AC Operating Requirements for ACT
Note 10: Voltage Range 5.0 is 5.0V
± 0.5V
Capacitance
VCC
TA = +25°CTA = −40°C to +85°C
Symbol
Parameter
(V)
CL = 50 pF
CL = 50 pF
Units
(Note 8)
Typ
Guaranteed Minimum
tS
Setup Time, HIGH or LOW
3.3
3.5
6.5
7.5
ns
Jn or Kn to CPn
5.0
2.0
4.5
5.0
tH
Hold Time, HIGH or LOW
3.3
−1.5
0
0
ns
Jn or Kn to CPn
5.0
−0.5
0.5
0.5
tW
Pulse Width
3.3
2.0
7.0
7.5
ns
CDn or SDn
5.0
2.0
4.5
5.0
tREC
Recovery Time
3.3
−2.5
0
0
ns
CDn or SDn to CPn
5.0
−1.5
0
0
VCC
TA = +25°CTA = −40°C to +85°C
Symbol
Parameter
(V)
CL = 50 pF
CL = 50 pF
Units
(Note 9)
Min
Typ
Max
Min
Max
fMAX
Maximum Clock Frequency
5.0
145
210
125
MHz
tPLH
Propagation Delay
5.0
4.0
7.0
11.0
3.5
13.0
ns
CPn to Qn or Qn
tPHL
Propagation Delay
5.0
3.0
6.0
10.0
2.5
11.5
ns
CPn to Qn or Qn
tPLH
Propagation Delay
5.0
2.5
5.5
9.5
2.0
10.5
ns
CDn or SDn to Qn or Qn
tPHL
Propagation Delay
5.0
2.5
6.0
10.0
2.0
11.5
ns
CDn or SDn to Qn or Qn
VCC
TA = +25°CTA = −40°C to +85°C
Symbol
Parameter
(V)
CL = 50 pF
CL = 50 pF
Units
(Note 10)
Typ
Guaranteed Minimum
tS
Setup Time, HIGH or LOW
5.0
0.5
2.0
2.5
ns
Jn or Kn to CPn
tH
Hold Time, HIGH or LOW
5.0
0
2.0
2.0
ns
Jn or Kn to CPn
tW
Pulse Width
5.0
3.0
5.0
6.0
ns
CPn or CDn or SDn
trec
Recovery Time
5.0
−2.5
0
0
ns
CDn or SDn to CPn
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
VCC = OPEN
CPD
Power Dissipation Capacitance
35.0
pF
VCC = 5.0V


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