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FW802A-DB Scheda tecnica(PDF) 1 Page - Agere Systems |
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FW802A-DB Scheda tecnica(HTML) 1 Page - Agere Systems |
1 / 24 page Data Sheet, Rev. 3 June 2001 FW802A Low-Power PHY IEEE* 1394A-2000 Two-Cable Transceiver/Arbiter Device Distinguishing Features I Compliant with IEEE Standard 1394a-2000, IEEE Standard for a High Performance Serial Bus Amendment 1. I Low-power consumption during powerdown or microlow-power sleep mode. I Supports extended BIAS_HANDSHAKE time for enhanced interoperability with camcorders. I While unpowered and connected to the bus, will not drive TPBIAS on a connected port even if receiving incoming bias voltage on that port. I Does not require external filter capacitors for PLL. I Does not require a separate 5 V supply for 5 V link controller interoperability. I Interoperable across 1394 cable with 1394 physical layers (PHY) using 5 V supplies. I Interoperable with 1394 link-layer controllers using 5 V supplies. I 1394a-2000 compliant common mode noise filter on incoming TPBIAS. I Powerdown features to conserve energy in battery- powered applications include: — Device powerdown pin. — Link interface disable using LPS. — Inactive ports power down. — Automatic microlow-power sleep mode during suspend. I Interface to link-layer controller supports Annex J electrical isolation as well as bus-keeper isolation. Features I Provides two fully compliant cable ports at 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s. I Fully supports OHCI requirements. I Supports arbitrated short bus reset to improve utilization of the bus. I Supports ack-accelerated arbitration and fly-by con- catenation. I Supports connection debounce. I Supports multispeed packet concatenation. I Supports PHY pinging and remote PHY access packets. I Fully supports suspend/resume. I Supports PHY-link interface initialization and reset. I Supports 1394a-2000 register set. I Supports LPS/link-on as a part of PHY-link inter- face. I Supports provisions of IEEE 1394-1995 Standard for a High Performance Serial Bus. I Fully interoperable with FireWire † implementation of IEEE 1394-1995. I Reports cable power fail interrupt when voltage at CPS pin falls below 7.5 V. I Separate cable bias and driver termination voltage supply for each port. I Meets Intel ‡ Mobile Power Guideline 2000. Other Features I 64-pin TQFP package. I Single 3.3 V supply operation. I Data interface to link-layer controller provided through 2/4/8 parallel lines at 50 Mbits/s. I 25 MHz crystal oscillator and PLL provide transmit/ receive data at 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s, and link-layer controller clock at 50 MHz. I Node power-class information signaling for system power management. I Multiple separate package signals provided for ana- log and digital supplies and grounds. * IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. † FireWire is a registered trademark of Apple Computer, Inc. ‡ Intel is a registered trademark of Intel Corporation. |
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