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FW801 Scheda tecnica(PDF) 8 Page - Agere Systems

Il numero della parte FW801
Spiegazioni elettronici  One-Cable Transceiver/Arbiter Device
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88
Agere Systems Inc.
Data Sheet, Rev. 1
June 2001
One-Cable Transceiver/Arbiter Device
FW801 PHY IEEE 1394A
46
SYSCLK
O
System Clock. SYSCLK provides a 49.152 MHz clock signal, which is
synchronized with the data transfers to the LLC.
31
TPA0+
Analog I/O Portn, Port Cable Pair A. TPAn is the port A connection to the twisted-
pair cable. Board traces from each pair of positive and negative differen-
tial signal pins should be kept matched and as short as possible to the
external load resistors and to the cable connector.
30
TPA0
Analog I/O Portn, Port Cable Pair A. TPAn is the port A connection to the twisted-
pair cable. Board traces from each pair of positive and negative differen-
tial signal pins should be kept matched and as short as possible to the
external load resistors and to the cable connector.
29
TPB0+
Analog I/O Portn, Port Cable Pair B. TPBn is the port B connection to the twisted-
pair cable. Board traces from each pair of positive and negative differen-
tial signal pins should be kept matched and as short as possible to the
external load resistors and to the cable connector.
28
TPB0
Analog I/O Portn, Port Cable Pair B. TPBn is the port B connection to the twisted-
pair cable. Board traces from each pair of positive and negative differen-
tial signal pins should be kept matched and as short as possible to the
external load resistors and to the cable connector.
32
TPBIAS0
Analog I/O Portn, Twisted-Pair Bias. TPBIAS provides the 1.86 V nominal bias
voltage needed for proper operation of the twisted-pair cable drivers and
receivers and for sending a valid cable connection signal to the remote
nodes.
5, 16, 22,
39
VDD
Digital Power. VDD supplies power to the digital portion of the device.
25, 33, 34
VDDA
Analog Circuit Power. VDDA supplies power to the analog portion of the
device.
12, 15, 21,
40, 47
VSS
Digital Ground. All VSS signals should be tied to the low-impedance
ground plane.
26, 27, 35,
36
VSSA
Analog Circuit Ground. All VSSA signals should be tied together to a low-
impedance ground plane.
43
XI
Crystal Oscillator. XI and XO connect to a 24.576 MHz parallel resonant
fundamental mode crystal. Although, when a 24.576 MHz clock source is
used, it can be connected to XI with XO left unconnected. The optimum
values for the external shunt capacitors are dependent on the specifica-
tions of the crystal used. The suggested values of 12 pF are appropriate
for crystal with 15 pF specified loads.
44
XO
Signal Information (continued)
Table 1. Signal Descriptions (continued)
Pin
Signal*
Type
Name/Description
* Active-low signals are indicated by “/” at the beginning of signal names, within this document.


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