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TS3005 Scheda tecnica(PDF) 3 Page - Touchstone Semiconductor Inc

Il numero della parte TS3005
Spiegazioni elettronici  A 1.55V to 5.25V, 1.35uA, 1.7ms to 33hrs Silicon Timer
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Produttore elettronici  TOUCHSTONE [Touchstone Semiconductor Inc]
Homepage  http://www.touchstonesemi.com
Logo TOUCHSTONE - Touchstone Semiconductor Inc

TS3005 Scheda tecnica(HTML) 3 Page - Touchstone Semiconductor Inc

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TS3005
TS3005DS r1p0
Page 3
RTFDS
ELECTRICAL CHARACTERISTICS
VDD = 3V, VPWM_CNTRL= VDD, RSET = 4.32MΩ, RLOAD(FOUT) = Open Circuit, CLOAD(FOUT) = 0pF, CLOAD(PWM) = 0pF, CPWM = 47pF, FDIV2:0 = 000 unless
otherwise noted. Values are at TA = 25°C unless otherwise noted. See Note 1.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage
VDD
1.55
5.25
V
Supply Current
IDD
CPWM = VDD
1.35
1.5
µA
-40°C
≤ T
A ≤ 85°C
1.9
1.47
1.7
-40°C
≤ T
A ≤ 85°C
2.1
FOUT Period
tFOUT
19.95
20.5
21.05
ms
-40°C
≤ T
A ≤ 85°C
19.4
21.5
FOUT Period Line
Regulation
Δt
FOUT/V
1.55
V ≤ V
DD ≤ 5.25V
0.17
%/V
FOUT Duty cycle
49
51
%
FOUT Period
Temperature
Coefficient
Δt
FOUT/ΔT
0.02
%/°C
PWMOUT Duty Cycle
DC(PWMOUT)
0.08
0.12
%
VPWM_CNTRL= 0V
0.02
0.03
PWMOUT Duty Cycle
Line Regulation
ΔDC(PWMOUT)/V
1.55V < VDD < 5.25V, FDIV2:0 = 000
-3
%
CPWM Sourcing Current
ICPWM
FDIV2:0 = 000, 001
930
1050
nA
-
40°C ≤ T
A ≤ 85°C
810
1150
FDIV2:0
000, 001
97
nA
UVLO Hysteresis
VUVLO
(VDD=1.55V) – (VDD_SHUTDOWN VOLTAGE)
150
250
mV
FOUT, PWMOUT
Rise Time
tRISE
See Note 2, CL = 15pF
10
ns
FOUT, PWMOUT
Fall Time
tFALL
See Note 2, CL = 15pF
10
ns
FOUT Jitter
See Note 3
0.001
%
RSET Pin Voltage
V(RSET)
0.3
V
FDIV Input Current
IFDIV
10
nA
-
40°C ≤ T
A ≤ 85°C
20
Maximum Oscillator
Frequency
Fosc
RSET= 360K
586
Hz
High Level Output
Voltage, FOUT and
PWMOUT
VDD - VOH
IOH = 1mA
160
mV
Low Level Output
Voltage, FOUT and
PWMOUT
VOL
IOL = 1mA
140
mV
Dead Time
TDT
FOUT edge falling and PWMOUT edge rising
106
ns
Note 1: All devices are 100% production tested at TA = +25°C and are guaranteed by characterization for TA = TMIN to TMAX, as specified.
Note 2: Output rise and fall times are measured between the 10% and 90% of the VDD power-supply voltage levels. The specification is based
on lab bench characterization and is not tested in production.
Note 3: Timing jitter is the ratio of the peak-to-peak variation of the period to the mean of the period. The specification is based on lab bench
characterization and is not tested in production.


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