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ADC083000 Scheda tecnica(PDF) 6 Page - Texas Instruments |
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ADC083000 Scheda tecnica(HTML) 6 Page - Texas Instruments |
6 / 14 page 5 signalpath.national.com/designer SIGNAL PATH designer 5 if the driving impedance is too high. If the driver stage is an amplifier, it has to settle after each transi- tion and prepare for the next sample. It must remain stable with the changing capacitive load. The input is sampled on every clock cycle, so an amplifier output would have approximately half a clock cycle to settle, which equates to 5 ns for a 100 MHz clock. If an ADC driver is not used and the input signal has high source impedance, then failure to properly match that to the relatively low ADC-input impedance can lead to inaccuracy and conversion errors. This matching is a key function of the amplifier and chan- nel-filter blocks. The amplifier provides the required output drive to charge the ADC sample-and-hold network, as well as enables other signal-conditioning functions such as level-shifting of the input signal into the range of the ADC input, and applying gain. The filter between the amplifier and ADC limits the noise bandwidth of the signal applied to the ADC, which would otherwise be the full bandwidth of the amplifier. It also isolates the capacitive load of the ADC input from the amplifier to maintain amplifier phase margin and stability, and attenuates the transient-charging glitches on the ADC input as the sample capacitance is switched. The filter should be designed to present a high-enough load to the amplifier to maximize amplifier-distortion performance while presenting low-enough impedance at high frequencies to the ADC to maximize the ADC’s performance. ADC Input Structures and the Choice of Driver ADC inputs may be single-ended or differential. The single-ended input is most commonly found on lower-speed and lower-resolution ADCs. It is limited by susceptibility to noise, distortion, and DC-offsets which lead to reduced accuracy and system performance. The differential-input ADC with complementary inputs provides immunity to common-mode errors, such as the noise injected by the sample-and-hold switching process since these errors appear on both inputs and are subtracted. Similarly, any even-order distortion such as the 2nd harmonic distortion (HD2) created by mismatched input impedances, or other asymmetry within the signal path, is also subtracted. In a low-voltage system where the undistorted signal swing is limited by the operating headroom of active devices along the signal path, a differential-analog signal enables twice the low distortion-voltage swing compared to a single-ended signal. Allowing for a 3 dB increase in noise, a differential stage will net 3 dB of extra SNR from the 6 dB extra signal power that a doubled output swing provides. This improved SNR contributes to improved Signal-to-Noise-and-Distortion (SINAD) and SNR in the overall system. For the single-ended-input ADC, Current Feedback (CFB) amplifiers are well suited due to their low distortion, high drive, and ability to deliver wide bandwidth at higher gains. The non- inverting-amplifier configuration (Figure 5a) has the advantage of very-high-input impedance, which is easy to match to any source-output impedance, RS, by adding a matching termination resistor, RT. By contrast, in Figure 5b, the input impedance, RS, of the inverting amplifier is RG//RT, where RG’s value interacts with RF in determining the gain. RT is optional and the input source can be directly matched to RG without RT. However, this can lead to a non-optimum value of RF for a particular gain, bandwidth, and gain flatness, especially in the case QH QS QS VIN+ VIN- VOUT+ VOUT- QS QS QS QH CH CH Source VOUT to ADC RF RG RT VIN RS ( ) ( ) = + 1 + RF RG AV RT RS RT Figure 4. Unbuffered ADC input sample and hold Figure 5a. Non-inverting single-ended amplifier SignalPathDesigner.indd 5 SignalPathDesigner.indd 5 9/5/07 3:24:33 PM 9/5/07 3:24:33 PM |
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