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ADC101S021 Scheda tecnica(PDF) 5 Page - Texas Instruments

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Il numero della parte ADC101S021
Spiegazioni elettronici  Single Channel, 0.5 to 1 Msps, 12-Bit A/D Converter
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Produttore elettronici  TI [Texas Instruments]
Homepage  http://www.ti.com
Logo TI - Texas Instruments

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ADC121S101
www.ti.com
SNAS304E – JANUARY 2006 – REVISED OCTOBER 2012
ADC121S101 Converter Electrical Characteristics
(1)(2) (continued)
The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 10 MHz to 20 MHz, CL = 15 pF, fSAMPLE = 500
ksps to 1 Msps, unless otherwise noted. Boldface limits apply for TA = -40°C to +125°C: all other limits TA = 25°C unless
otherwise noted.
Symbol
Parameter
Conditions
Typical
Limits(2)
Units
DIGITAL INPUT CHARACTERISTICS
VA = +5.25V
2.4
V (min)
VIH
Input High Voltage
VA = +3.6V
2.1
V (min)
VA = +5V
0.8
V (max)
VIL
Input Low Voltage
VA = +3V
0.4
V (max)
IIN
Input Current
VIN = 0V or VA
±0.1
±1
µA (max)
CIND
Digital Input Capacitance
2
4
pF (max)
DIGITAL OUTPUT CHARACTERISTICS
ISOURCE = 200 µA
VA − 0.07
VA − 0.2
V (min)
VOH
Output High Voltage
ISOURCE = 1 mA
VA − 0.1
V
ISINK = 200 µA
0.03
0.4
V (max)
VOL
Output Low Voltage
ISINK = 1 mA
0.1
V
IOZH,
TRI-STATE Leakage
±0.1
±10
µA (max)
IOZL
Current
TRI-STATE Output
COUT
2
4
pF (max)
Capacitance
Output Coding
Straight (Natural) Binary
POWER SUPPLY CHARACTERISTICS
2.7
V (min)
VA
Supply Voltage
5.25
V (max)
VA = +5.25V, fSAMPLE = 1 Msps
2.0
3.2
mA (max)
Supply Current, Normal
Mode (Operational, CS low) V
A = +3.6V, fSAMPLE = 1 Msps
0.6
1.5
mA (max)
IA
fSCLK = 0 MHz, VA = +5V, fSAMPLE = 0 ksps
500
nA
Supply Current, Shutdown
(CS high)
fSCLK = 20 MHz, VA = +5V, fSAMPLE = 0 ksps
60
µA
Power Consumption,
VA = +5V
10
16
mW (max)
Normal Mode (Operational,
VA = +3V
2.0
4.5
mW (max)
CS low)
PD
fSCLK = 0 MHz, VA = +5V, fSAMPLE = 0 ksps
2.5
µW
Power Consumption,
Shutdown (CS high)
fSCLK = 20 MHz, VA = +5V, fSAMPLE = 0 ksps
300
µW
AC ELECTRICAL CHARACTERISTICS
10
MHz (min)
fSCLK
Clock Frequency(3)
See(4)
20
MHz (max)
500
ksps (min)
fS
Sample Rate
See(4)
1
Msps (max)
40
% (min)
DC
SCLK Duty Cycle
fSCLK = 20 MHz
50
60
% (max)
Minimum Time Required for
tACQ
350
ns (max)
Acquisition
tQUIET
See(5)
50
ns (min)
tAD
Aperture Delay
3
ns
tAJ
Aperture Jitter
30
ps
(3)
This condition is for fSCLK = 20 MHz.
(4)
This is the frequency range over which the electrical performance is guaranteed. The device is functional over a wider range which is
specified under Operating Ratings.
(5)
Minimum Quiet Time required by bus relinquish and the start of the next conversion.
Copyright © 2006–2012, Texas Instruments Incorporated
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