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ADV7202 Scheda tecnica(PDF) 11 Page - Analog Devices |
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ADV7202 Scheda tecnica(HTML) 11 Page - Analog Devices |
11 / 26 page REV. PrB PRELIMINARY TECHNICAL DATA ADV7202 –11– Video Clamping and AGC Control When Analog signal clamping is required the input signal should be AC coupled to the input via a capacitor, the clamping control is via the MPU port. The AGC is implemented digitally. For correct operation the user must program the clamp value to which the signal has been clamped into the ADV7202 I 2C Register. This allows the user to specify which signal level is unaffected by the AGC. The digital output signal will be a function of the ADC output, the AGC Gain, and the Clamp Level, and can be repre- sented as follows, (1) D_OUT will be a 10-bit number (0–1023), the AGC Gain defaults to 2 and can have a value between 0 to 7.99. The Clamp Level is a 10-bit number (0–1023) although only the top eight bits of clamp level are specified in the I 2C Register; the ADC value can be regarded as a 10-bit number (0–1023) for the equation. It should be noted that the ADC resolution is 12 bits. The above equation is used to give a basic perspective, and is mathematically correct. When the clamps are operational, the operation described by Equation (1) is how the ADV7202 ensures that the level to which the user is clamping is unaffected by the AGC loop. When no clamps are operational, the operation should be regarded as a straightforward gain-and-level shift. Equation (1) maps the ADC input voltage range to its output. AGC Gain The AGC Gain can be set to a value from 0 to 7.9. The AGC Gain Register holds a 12-bit number that corresponds to the required gain. The first three MSBs hold the gain integer value while the remaining nine bits hold the gain fractional value. Example: The user requires a gain of 3.65. The first three bits give the integer value 3, hence these will be set to ‘0 1 1.’ The remaining nine bits will have to be set to give the fractional value 0.65, 512 0.65 = 333 = ‘10100110 1.’ From Equation (2) it can be seen that the Clamp Level is taken from the signal before AGC is applied and then added on again afterwards; hence, if the AGC Gain is set to a value of one, the result would be as follows, (AGC Gain = 1) D Clamp Level ADC _OUT = ADC - Clamp Level += (2) FUNCTIONAL DESCRIPTION Clamp and AGC Control The ADV7202 has a front end 3-channel clamp control. In order to perform an accurate AGC gain operation, it is neces- sary to know to what level the user is clamping the black level; this value is programmable in Clamp Register 0 CR00–CR07. Each channel has a fine and coarse clamp; the clamp direction and its duration are programmable. Synchronization of the clamps and AGC to the input signal is possible using the SYNC_IN con- trol pin and setting mode register CR14 to Logic Level “1.” Using this method, it is possible to ensure that AGC and clamping are only applied outside the active video area. Control Signals The function and operation of the SYNC_IN signal is described in the Clamp Control section. The SYNC_OUT will go high while Cr data from a YCrCb data stream or C data from a Y/C data stream has been output on DOUT[9:0]. See Figure 1 to Figure 3. I 2C Filter A selectable internal I 2C filter allows significant noise reduction on the I2C interface. In setting ALSB high, the input bandwidth on the I 2C lines is reduced and pulses of less than 50 ns are not passed to the I 2C controller. Setting ALSB low allows greater input bandwidth on the I2C lines. XTAL0 CVBS DAC_DATA [9:0] SYNC_OUT CVBS CVBS CVBS CVBS CVBS CVBS Figure 1. SYNC_OUT Output Timing, CVBS Input XTAL0 DAC_DATA [9:0] SYNC_OUT YC YC Y C Y Figure 2. SYNC_OUT Output Timing, Y/C (S-VIDEO) Input D Clamp Level _OUT = ADC Gain ADC – Clamp Level × () []+ |
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