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ADMC331BST Scheda tecnica(PDF) 8 Page - Analog Devices |
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ADMC331BST Scheda tecnica(HTML) 8 Page - Analog Devices |
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8 / 36 page  ADMC331 –8– REV. B BUS EXCHANGE DATA ADDRESS GENERATOR #2 DATA ADDRESS GENERATOR #1 14 14 24 16 6 R BUS 16 COMPANDING CIRCUITRY DMA BUS PMA BUS DMD BUS PMD BUS PROGRAM SEQUENCER INSTRUCTION REGISTER INPUT REGS OUTPUT REGS SHIFTER INPUT REGS OUTPUT REGS MAC INPUT REGS OUTPUT REGS ALU SERIAL PORT 0 RECEIVE REG TRANSMIT REG CONTROL LOGIC DM RAM 1K 16 PM ROM 2K 24 PM RAM 2K 24 SERIAL PORT 1 RECEIVE REG TRANSMIT REG 5 TIMER Figure 3. DSP Core Block Diagram DSP CORE ARCHITECTURE OVERVIEW Figure 3 is an overall block diagram of the DSP core of the ADMC331, which is based on the fixed-point ADSP-2171. The flexible architecture and comprehensive instruction set of the ADSP-2171 allows the processor to perform multiple operations in parallel. In one processor cycle (38.5 ns with a 13 MHz CLKIN) the DSP core can: • Generate the next program address. • Fetch the next instruction. • Perform one or two data moves. • Update one or two data address pointers. • Perform a computational operation. This all takes place while the processor continues to: • Receive and transmit through the serial ports. • Decrement the interval timer. • Generate three-phase PWM waveforms for a power inverter. • Generate two signals using the 8-bit auxiliary PWM timers. • Acquire four analog signals. • Decrement the watchdog timer. The processor contains three independent computational units: the arithmetic and logic unit (ALU), the multiplier/accumulator (MAC) and the shifter. The computational units process 16-bit data directly and have provisions to support multiprecision com- putations. The ALU performs a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs single-cycle multiply, multiply/add, multiply/ subtract operations with 40 bits of accumulation. The shifter performs logical and arithmetic shifts, normalization, denormalization and derive exponent operations. The shifter can be used to effi- ciently implement numeric format control including floating- point representations. The internal result (R) bus directly connects the computational units so that the output of any unit may be the input of any unit on the next cycle. A powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these computa- tional units. The sequencer supports conditional jumps and subroutine calls and returns in a single cycle. With internal loop counters and loop stacks, the ADMC331 executes looped code with zero overhead; no explicit jump instructions are required to maintain the loop. Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches from data memory and program memory. Each DAG maintains and updates four ad- dress pointers (I registers). Whenever the pointer is used to access data (indirect addressing), it is post-modified by the value in one of four modify (M registers). A length value may be associated with each pointer (L registers) to implement auto- matic modulo addressing for circular buffers. The circular buff- ering feature is also used by the serial ports for automatic data transfers to and from on-chip memory. DAG1 generates only data memory address but provides an optional bit-reversal capability. DAG2 may generate either program or data memory addresses, but has no bit-reversal capability. Efficient data transfer is achieved with the use of five internal buses: • Program Memory Address (PMA) Bus • Program Memory Data (PMD) Bus • Data Memory Address (DMA) Bus • Data Memory Data (DMD) Bus • Result (R) Bus |
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