Motore di ricerca datesheet componenti elettronici
  Italian  ▼
ALLDATASHEETIT.COM

X  

ADMC326 Scheda tecnica(PDF) 10 Page - Analog Devices

Il numero della parte ADMC326
Spiegazioni elettronici  28-Lead ROM-Based DSP Motor Controller
Download  31 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

ADMC326 Scheda tecnica(HTML) 10 Page - Analog Devices

Back Button ADMC326 Datasheet HTML 6Page - Analog Devices ADMC326 Datasheet HTML 7Page - Analog Devices ADMC326 Datasheet HTML 8Page - Analog Devices ADMC326 Datasheet HTML 9Page - Analog Devices ADMC326 Datasheet HTML 10Page - Analog Devices ADMC326 Datasheet HTML 11Page - Analog Devices ADMC326 Datasheet HTML 12Page - Analog Devices ADMC326 Datasheet HTML 13Page - Analog Devices ADMC326 Datasheet HTML 14Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 31 page
background image
ADMC326
–10–
REV. A
shown in Figure 4. The crystal should be connected across the
CLKIN and XTAL pins, with two capacitors as shown in Figure 4.
A parallel-resonant, fundamental frequency, microprocessor-grade
crystal should be used. A clock output signal (CLKOUT) is
generated by the processor at the processor’s cycle rate of twice
the input frequency.
Reset
The ADMC326 DSP core and peripherals must be correctly re-
set when the device is powered up to assure proper initialization.
The ADMC326 contains an integrated power-on reset (POR)
circuit that provides a complete system reset on power-up and
power-down. The POR circuit monitors the voltage on the
ADMC326 VDD pin and holds the DSP core and peripherals in
reset while VDD is less than the threshold voltage level, VRST.
When this voltage is exceeded, the ADMC326 is held in reset
for an additional 2
16 DSP clock cycles (t
RST in Figure 5). On
power-down, when the voltage on the VDD pin falls below
VRST–VHYST, the ADMC326 will be reset. Also, if the external
RESET pin is actively pulled low at any time after power-up, a
complete hardware reset of the ADMC326 is initiated.
VRST
VDD
RESET
VRST – VHYST
tRST
Figure 5. Power-On Reset Operation
The ADMC326 reset sets all internal stack pointers to the empty
stack condition, masks all interrupts, clears the MSTAT register
and performs a full reset of all of the motor control peripherals.
Following a power-up, it is possible to initiate a DSP core and
motor control peripheral reset by pulling the
RESET pin low.
The
RESET signal must meet the minimum pulsewidth specifi-
cation, tRSP. Following the reset sequence, the DSP core starts
executing code from the internal PM ROM located at 0x0800.
DSP Control Registers
The DSP core has a system control register, SYSCNTL, memory
mapped at DM (0x3FFF). SPORT1 is configured as a serial
port when Bit 10 is set, or as flags and interrupt lines when this
bit is cleared. For proper operation of the ADMC326, all other
bits in this register must be cleared.
The DSP core has a wait state control register, MEMWAIT,
memory mapped at DM (0x3FFE). The default value of this
register is 0xFFFF. For proper operation of the ADMC326 this
register must be set to 0x8000.
The configuration of both the SYSCNTL and MEMWAIT
registers of the ADMC326 are shown at the end of this data sheet.
THREE-PHASE PWM CONTROLLER
Overview
The PWM generator block of the ADMC326 is a flexible, pro-
grammable, three-phase PWM waveform generator that can be
programmed to generate the required switching patterns to drive
a three-phase voltage source inverter for ac induction motors
(ACIM) or permanent magnet synchronous motors (PMSM).
In addition, the PWM block contains special functions that consid-
erably simplify the generation of the required PWM switching
patterns for control of electronically commutated motors (ECM)
or brushless dc motors (BDCM).
The PWM generator produces three pairs of active high PWM
signals on the six PWM output pins (AH, AL, BH, BL, CH,
and CL). The six PWM output signals consist of three high side
drive signals (AH, BH, and CH) and three low side drive signals
(AL, BL, and CL). The switching frequency, dead time and
minimum pulsewidths of the generated PWM patterns are pro-
grammable using respectively the PWMTM, PWMDT, and
PWMPD registers. In addition, three registers (PWMCHA,
PWMCHB, and PWMCHC) control the duty cycles of the three
pairs of PWM signals.
Each of the six PWM output signals can be enabled or disabled
by separate output enable bits of the PWMSEG register. In
addition, three control bits of the PWMSEG register permit
crossover of the two signals of a PWM pair for easy control of
ECM or BDCM. In crossover mode, the PWM signal destined
for the high side switch is diverted to the complementary low
side output, and the signal destined for the low side switch is
diverted to the corresponding high side output signal.
In many applications, there is a need to provide an isolation
barrier in the gate-drive circuits that turn on the power devices
of the inverter. In general, there are two common isolation tech-
niques: optical isolation using optocouplers, and transformer
isolation using pulse transformers. The PWM controller of the
ADMC326 permits mixing of the output PWM signals with a
high frequency chopping signal to permit an easy interface to
such pulse transformers. The features of this gate-drive chop-
ping mode can be controlled by the PWMGATE register. There
is an 8-bit value within the PWMGATE register that directly
controls the chopping frequency. In addition, high frequency
chopping can be independently enabled for the high side and the
low side outputs using separate control bits in the PWMGATE
register.
The PWM generator is capable of operating in two distinct
modes: single update mode or double update mode. In single
update mode, the duty cycle values are programmable only once
per PWM period, so that the resultant PWM patterns are sym-
metrical about the midpoint of the PWM period. In the double
update mode, a second updating of the PWM duty cycle values
is implemented at the midpoint of the PWM period. In this mode,
it is possible to produce asymmetrical PWM patterns that pro-
duce lower harmonic distortion in three-phase PWM inverters.
This technique also permits the closed-loop controller to change
the average voltage applied to the machine winding at a faster
rate, allowing wider closed-loop bandwidths to be achieved. The
operating mode of the PWM block (single or double update mode)
is selected by a control bit in MODECTRL register.
The PWM generator of the ADMC326 also provides an internal
signal that synchronizes the PWM switching frequency to the
A/D operation. In single update mode, a PWMSYNC pulse is
produced at the start of each PWM period. In double update
mode, an additional PWMSYNC pulse is produced at the mid-
point of each PWM period. The width of the PWMSYNC pulse
is programmable through the PWMSYNCWT register.
The PWM signals produced by the ADMC326 can be shut off
in a number of different ways. First, there is a dedicated asyn-
chronous PWM shutdown pin,
PWMTRIP, which, when brought
LO, instantaneously places all six PWM outputs in the OFF


Codice articolo simile - ADMC326

Produttore elettroniciIl numero della parteScheda tecnicaSpiegazioni elettronici
logo
Analog Devices
ADMC326 AD-ADMC326_15 Datasheet
240Kb / 32P
   28-Lead ROM-Based DSP Motor Controller
REV. C
More results

Descrizione simile - ADMC326

Produttore elettroniciIl numero della parteScheda tecnicaSpiegazioni elettronici
logo
Analog Devices
ADMC326 AD-ADMC326_15 Datasheet
240Kb / 32P
   28-Lead ROM-Based DSP Motor Controller
REV. C
ADMC328 AD-ADMC328_15 Datasheet
248Kb / 32P
   28-Lead ROM-Based DSP Motor Controller with Current Sense
REV. C
ADMC328 AD-ADMC328 Datasheet
234Kb / 32P
   28-Lead ROM-Based DSP Motor Controller with Current Sense
REV. B
ADMCF326 AD-ADMCF326_15 Datasheet
528Kb / 36P
   28-Lead Flash Memory DSP Motor Controller
REV. B
ADMCF326 AD-ADMCF326 Datasheet
242Kb / 36P
   28-Lead Flash Memory DSP Motor Controller
REV. 0
ADMCF326BRZ AD-ADMCF326BRZ Datasheet
528Kb / 36P
   28-Lead Flash Memory DSP Motor Controller
REV. B
ADMCF327 AD-ADMCF327 Datasheet
253Kb / 36P
   28-Lead Flash Memory DSP Switched Reluctance Motor Controller
REV. 0
ADMCF327 AD-ADMCF327_15 Datasheet
241Kb / 36P
   28-Lead Flash Memory DSP Switched Reluctance Motor Controller
REV. 0
ADMC300 AD-ADMC300 Datasheet
297Kb / 42P
   High Performance DSP-Based Motor Controller
REV. B
ADMC300 AD-ADMC300_15 Datasheet
296Kb / 42P
   High Performance DSP-Based Motor Controller
REV. B
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31


Scheda tecnica Scarica

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEETIT.COM
Lei ha avuto il aiuto da alldatasheet?  [ DONATE ] 

Di alldatasheet   |   Richest di pubblicita   |   contatti   |   Privacy Policy   |   scambio Link   |   Ricerca produttore
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com