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ADM3202AN Scheda tecnica(PDF) 6 Page - Analog Devices

Il numero della parte ADM3202AN
Spiegazioni elettronici  Low Power, 3.3 V, RS-232 Line Drivers/Receivers
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
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ADM3202AN Scheda tecnica(HTML) 6 Page - Analog Devices

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ADM3202/ADM3222/ADM1385
–6–
REV. A
GENERAL DESCRIPTION
The ADM3202/ADM3222/ADM1385 are RS-232 line drivers/
receivers. Step-up voltage converters coupled with level shifting
transmitters and receivers allow RS-232 levels to be developed
while operating from a single +3.3 V supply.
CMOS technology is used to keep the power dissipation to an
absolute minimum, allowing maximum battery life in portable
applications.
The ADM3202/ADM3222/ADM1385 is a modification, en-
hancement and improvement to the AD230–AD241 family and
its derivatives. It is essentially plug-in compatible and does not
have materially different applications.
CIRCUIT DESCRIPTION
The internal circuitry consists of three main sections. These are:
1. A charge pump voltage converter
2. 3.3 V logic to EIA-232 transmitters
3. EIA-232 to 5 V logic receivers.
Charge Pump DC-DC Voltage Converter
The charge pump voltage converter consists of a 200 kHz oscil-
lator and a switching matrix. The converter generates a
±6.6 V
supply from the input +3.3 V level. This is done in two stages
using a switched capacitor technique as illustrated below. First,
the +3.3 V input supply is doubled to +6.6 V using capacitor
C1 as the charge storage element. The +6.6 V level is then
inverted to generate –6.6 V using C2 as the storage element. C3
is shown connected between V+ and VCC, but is equally effec-
tive if connected between V+ and GND.
Capacitors C3 and C4 are used to reduce the output ripple.
Their values are not critical and can be increased if desired.
Capacitor C3 is shown connected between V+ and VCC. It is
also acceptable to connect this capacitor between V+ and GND.
If desired, larger capacitors (up to 10
µF) can be used for
capacitors C1–C4.
+3.3V TO +6.6V
VOLTAGE
DOUBLER
C1+
C1–
C5
0.1 F
+
VCC
V+
0.1 F
10V
+
+
C3
0.1 F
6.3V
+3.3V INPUT
+6.6V TO –6.6V
VOLTAGE
INVERTER
C2+
C2–
+
V–
0.1 F
10V
+
C4
0.1 F
10V
T1OUT
T1IN
T2OUT
T2IN
EIA/TIA-232
OUTPUTS
R1OUT
R2OUT
R1IN
R2IN
EIA/TIA-232
INPUTS*
CMOS
INPUTS
CMOS
OUTPUTS
ADM3202
GND
*INTERNAL 5k
PULL-DOWN RESISTOR
ON EACH RS-232 INPUT
+3.3V TO +6.6V
VOLTAGE
DOUBLER
C1+
C1–
C5
0.1 F
+
VCC
V+
0.1 F
10V
+
+
C3
0.1 F
6.3V
+3.3V INPUT
+6.6V TO –6.6V
VOLTAGE
INVERTER
C2+
C2–
+
V–
0.1 F
10V
+
C4
0.1 F
10V
T1OUT
T1IN
T2OUT
T2IN
EIA/TIA-232
OUTPUTS
R1OUT
R2OUT
R1IN
R2IN
EIA/TIA-232
INPUTS*
CMOS
INPUTS
CMOS
OUTPUTS
ADM3222
GND
*INTERNAL 5k
PULL-DOWN RESISTOR
ON EACH RS-232 INPUT
T1
T2
R2
R1
T1
T2
R2
R1
EN
SD
+3.3V TO +6.6V
VOLTAGE
DOUBLER
C1+
C1–
C5
0.1 F
+
VCC
V+
0.1 F
10V
+
C3
0.1 F
6.3V
+3.3V INPUT
+6.6V TO –6.6V
VOLTAGE
INVERTER
C2+
C2–
+
V–
0.1 F
10V
+
C4
0.1 F
10V
T1OUT
T1IN
T2OUT
T2IN
EIA/TIA-232
OUTPUTS
R1OUT
R2OUT
R1IN
R2IN
EIA/TIA-232
INPUTS*
CMOS
INPUTS
CMOS
OUTPUTS
ADM1385
GND
*INTERNAL 5k
PULL-DOWN RESISTOR
ON EACH RS-232 INPUT
T1
T2
R2
R1
DD
SD
+
Figure 8. Typical Operating Circuits
1 s/DIV
T1IN
2V/DIV
T1OUT
5V/DIV
Figure 7. 230 kbps Data Transmission


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