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ADM1232ARM Scheda tecnica(PDF) 2 Page - Analog Devices

Il numero della parte ADM1232ARM
Spiegazioni elettronici  Microprocessor Supervisory Circuit
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Homepage  http://www.analog.com
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ADM1232ARM Scheda tecnica(HTML) 2 Page - Analog Devices

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–2–
REV. B
ADM1232–SPECIFICATIONS (V
CC = Full Operating Range, TA = TMIN to TMAX unless otherwise noted)
Parameter
Min
Typ
Max
Units
Test Conditions/Comments
TEMPERATURE
–40
+85
°CT
A = TMIN to TMAX
POWER SUPPLY
Voltage
4.5
5.0
5.5
V
Current
20
50
µAV
IL, VIH = CMOS Levels
200
500
µAV
IL, VIH = TTL Levels
STROBE AND PB RESET INPUTS
Input High Level
2.0
VCC + 0.3
V
Input Low Level
–0.3
+0.8
V
INPUT LEAKAGE CURRENT
(
STROBE, TOLERANCE)
–1.0
+1.0
µA
TD
1.6
µA
OUTPUT CURRENT
RESET
8
10
mA
When VCC Is at 4.5 V–5.5 V
RESET, RESET
–8
–12
mA
When VCC Is at 4.5 V–5.5 V
OUTPUT VOLTAGE
RESET/RESET
VCC – 0.5 VCC – 0.1
V
While sourcing less than 500
µA, RESET remains
within 0.5 V of VCC on power-down until VCC
drops below 2.0 V. While sinking less than
500
µA, RESET remains within 0.5 V of GND
on power-down until VCC drops below 2.0 V.
RESET/RESET High Level
0.4
V
RESET/RESET Low Level
2.4
V
1 V OPERATION
RESET Output Voltage
VCC – 0.1
V
While Sourcing Less than 50
µA
RESET Output Voltage
0.1
V
While Sinking Less than 50
µA
VCC TRIP POINT
5%
4.5
4.62
4.74
V
TOLERANCE = GND
10%
4.25
4.37
4.49
V
TOLERANCE = VCC
CAPACITANCE
Input (
STROBE, TOLERANCE)
5
pF
TA = +25°C
Output (RESET,
RESET)7
pF
TA = +25°C
PB RESET
Time
20
ms
PB RESET Must Be Held Low for a Minimum
Delay
1
4
20
ms
of 20 ms to Guarantee a Reset
RESET ACTIVE TIME
250
610
1000
ms
STROBE
Pulse Width
70
ns
Timeout Period
62.5
150
250
ms
TD = 0 V
250
600
1000
ms
TD = Floating
500
1200
2000
ms
TD = VCC
VCC
Fall Time
10
µS
Guaranteed by Design
Rise Time
0
µS
Guaranteed by Design
VCC FAIL DETECT TO RESET OUTPUT DELAY
RESET AND
RESET Are Logically Correct
50
µs
After VCC Falls Below the Set Tolerance Voltage
(Figure 5)
250
610
1000
ms
After VCC Rises Above the Set Tolerance Voltage
Specifications subject to change without notice.


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