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ADF4117BCP Scheda tecnica(PDF) 5 Page - Analog Devices |
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ADF4117BCP Scheda tecnica(HTML) 5 Page - Analog Devices |
5 / 20 page ADF4116/ADF4117/ADF4118 –5– REV. 0 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1FLO Fast Lock Switch Output. This can be used to switch an external resistor to change the loop filter band- width. This will speed up locking of the PLL. 2 CP Charge Pump Output. When enabled, this provides the ±I CP to the external loop filter, which in turn drives the external VCO. 3 CPGND Charge Pump Ground. This is the ground return path for the charge pump. 4 AGND Analog Ground. This is the ground return path for the prescaler. 5RFINB Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small bypass capacitor, typically 100 pF. See Figure 22. 6RFINA Input to the RF Prescaler. This small signal input is normally ac-coupled from the VCO. 7AVDD Analog Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD. 8 REFIN Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of 100 k Ω. See Figure 21. The oscillator input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled. 9 DGND Digital Ground. 10 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three- state mode. Taking the pin high will power up the device depending on the status of the power-down bit F2. 11 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 21-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. 12 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high impedance CMOS input. 13 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. 14 MUXOUT This multiplexer output allows either the Lock Detect, the scaled RF or the scaled Reference Frequency to be accessed externally. 15 DVDD Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD. 16 VP Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it can be set to 5 V and used to drive a VCO with a tuning range of up to 6 V. PIN CONFIGURATIONS TSSOP TOP VIEW (Not to Scale) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 FLO VP ADF4116 ADF4117 ADF4118 CP DVDD CPGND MUXOUT AGND LE RFINB DATA RFINA CLK AVDD CE REFIN DGND Chip Scale Package TOP VIEW (Not to Scale) CPGND AGND AGND RFINB RFINA MUXOUT LE DATA CLK CE ADF4116 ADF4117 ADF4118 1 2 3 4 5 15 14 13 12 11 |
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