ADEL2020

REV. A

–9–

GENERAL DESIGN CONSIDERATIONS

The ADEL2020 is a current feedback amplifier optimized for

use in high performance video and data acquisition systems.

Since it uses a current feedback architecture, its closed-loop

bandwidth depends on the value of the feedback resistor. The

–3 dB bandwidth is also somewhat dependent on the power

supply voltage. Lowering the supplies increases the values of in-

ternal capacitances, reducing the bandwidth. To compensate for

this, smaller values of feedback resistor are used at lower supply

voltages.

POWER SUPPLY BYPASSING

Adequate power supply bypassing can be critical when optimiz-

ing the performance of a high frequency circuit. Inductance in

the power supply leads can contribute to resonant circuits that

produce peaking in the amplifier’s response. In addition, if large

current transients must be delivered to the load, then bypass ca-

pacitors (typically greater than 1

µF) will be required to provide

the best settling time and lowest distortion. Although the rec-

ommended 0.1

µF power supply bypass capacitors will be suffi-

cient in most applications, more elaborate bypassing (such as

using two paralleled capacitors) may be required in some cases.

CAPACITIVE LOADS

When used with the appropriate feedback resistor, the ADEL2020

can drive capacitive loads exceeding 1000 pF directly without

oscillation. Another method of compensating for large load ca-

pacitance is to insert a resistor in series with the loop output. In

most cases, less than 50

Ω is all that is needed to achieve an

extremely flat gain response.

OFFSET NULLING

A 10 k

Ω pot connected between Pins 1 and 5, with its wiper

connected to V+, can be used to trim out the inverting input

current (with about

±20 µA of range). For closed-loop gains

above about 5, this may not be sufficient to trim the output off-

set voltage to zero. Tie the pot’s wiper to ground through a

large value resistor (50 k

Ω for ±5 V supplies, 150 kΩ for ±15 V

supplies) to trim the output to zero at high closed-loop gains.

OPERATION AS A VIDEO LINE DRIVER

The ADEL2020 is designed to offer outstanding performance at

closed-loop gains of one or greater. At a gain of 2, the ADEL2020

makes an excellent video line driver. The low differential gain

and phase errors and wide –0.1 dB bandwidth are nearly inde-

pendent of supply voltage and load. For applications requiring

widest 0.1 dB bandwidth, it is recommended to use 715

Ω feed-

back and gain resistors. This will result in about 0.05 dB of

peaking and a –0.1 dB bandwidth of 30 MHz on

±15 V supplies.

DISABLE MODE

By pulling the voltage on Pin 8 to common (0 V), the ADEL2020

can be put into a disabled state. In this condition, the supply

current drops to less than 2.8 mA, the output becomes a high

impedance, and there is a high level of isolation from input to

output. In the case of a line driver for example, the output im-

pedance will be about the same as for a 1.5 k

Ω resistor (the

feedback plus gain resistors) in parallel with a 13 pF capacitor

(due to the output) and the input to output isolation will be bet-

ter than 50 dB at 10 MHz.

Leaving the disable pin disconnected (floating) will leave the

part in the enabled state.

In cases where the amplifier is driving a high impedance load,

the input to output isolation will decrease significantly if the in-

put signal is greater than about 1.2 V peak to peak. The isola-

tion can be restored to the 50 dB level by adding a dummy load

(say 150

Ω) at the amplifier output. This will attenuate the

feedthrough signal. (This is not an issue for multiplexer applica-

tions where the outputs of multiple ADEL2020s are tied to-

gether as long as at least one channel is in the ON state.) The

input impedance of the disable pin is about 35 k

Ω in parallel

with a few pF. When grounded, about 50

µA flows out of the

disable pin for

±5 V supplies.

Break before make operation is guaranteed by design. If driven

by standard CMOS logic, the disable time (until the output is

high impedance), is about 100 ns and the enable time (to low

impedance output) is about 160 ns. Since it has an internal pull-

up resistor of about 35 k

Ω, the ADEL2020 can be used with

open drain logic as well. In this case, the enable time is in-

creased to about 1

µs.

If there is a nonzero voltage present on the amplifier’s output

at the time it is switched to the disabled state, some additional

decay time will be required for the output voltage to relax to

zero. The total time for the output to go to zero will generally

be about 250 ns and is somewhat dependent on the load

impedance.