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FAN54011UCX(1) Scheda tecnica(PDF) 7 Page - Fairchild Semiconductor |
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FAN54011UCX(1) Scheda tecnica(HTML) 7 Page - Fairchild Semiconductor |
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7 / 36 page /3487/7/FAN54011UCX(1).png) © 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5401X Family • Rev. 1.0.4 7 Electrical Specifications Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA; VBUS=5.0 V; HZ_MODE; OPA_MODE=0; (Charge Mode); SCL, SDA, OTG=0 or 1.8 V; and typical values are for TJ=25°C. Symbol Parameter Conditions Min. Typ. Max. Unit Input Power Source Detection VIN(MIN)1 VBUS Input Voltage Rising To Initiate and Pass VBUS Validation 4.29 4.42 V VIN(MIN)2 Minimum VBUS During Charge During Charging 3.71 3.94 V tVBUS_VALID VBUS Validation Time 30 ms Special Charger (VBUS) (FAN54013, FAN54014) VSP Special Charger Setpoint Accuracy –3 +3 % Input Current Limit IINLIM Input Current Limit Threshold IIN Set to 100 mA 88 93 98 mA IIN Set to 500 mA 450 475 500 VREF Bias Generator VREF Bias Regulator Voltage VBUS > VIN(MIN) or VBAT > VBAT(MIN) 6.5 V Short-Circuit Current Limit 20 mA Battery Recharge Threshold VRCH Recharge Threshold Below V(OREG) 100 120 150 mV Deglitch Time VBAT Falling Below VRCH Threshold 130 ms STAT Output VSTAT(OL) STAT Output Low ISTAT=10 mA 0.4 V ISTAT(OH) STAT High Leakage Current VSTAT=5 V 1 A Battery Detection IDETECT Battery Detection Current before Charge Done (Sink Current) (5) Begins after Termination Detected and VBAT < VOREG –VRCH –0.80 mA tDETECT Battery Detection Time 262 ms Sleep Comparator VSLP Sleep-Mode Entry Threshold, VBUS – VBAT 2.3 V < VBAT < VOREG, VBUS Falling 0 0.04 0.10 V tSLP_EXIT Deglitch Time for VBUS Rising Above VBAT by VSLP Rising Voltage 30 ms Power Switches (see Figure 3) RDS(ON) Q3 On Resistance (VBUS to PMID) IIN(LIMIT)=500 mA 180 250 mΩ Q1 On Resistance (PMID to SW) 130 225 Q2 On Resistance (SW to GND) 150 225 Charger PWM Modulator fSW Oscillator Frequency 2.7 3.0 3.3 MHz DMAX Maximum Duty Cycle 100 % DMIN Minimum Duty Cycle 0 % ISYNC Synchronous to Non-Synchronous Current Cut-Off Threshold (6) Low-Side MOSFET (Q2) Cycle-by- Cycle Current Limit 140 mA Continued on the following page… |
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