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AD841KQ Scheda tecnica(PDF) 6 Page - Analog Devices |
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AD841KQ Scheda tecnica(HTML) 6 Page - Analog Devices |
6 / 8 page AD841 REV. B –6– INPUT CONSIDERATIONS An input resistor (RIN in Figure 20) is recommended in circuits where the input to the AD841 will be subjected to transient or continuous overload voltages exceeding the ±6 V maximum dif- ferential limit. This resistor provides protection for the input transistors by limiting the maximum current that can be forced into the input. For high performance circuits it is recommended that a resistor (RB in Figures 19 and 20) be used to reduce bias current errors by matching the impedance at each input. The output voltage error caused by the offset current is more than an order of mag- nitude less than the error present if the bias current error is not removed. AD841 SETTLING TIME Figures 22 and 24 show the settling performance of the AD841 in the test circuit shown in Figure 23. Settling time is defined as: The interval of time from the application of an ideal step function input until the closed-loop amplifier output has entered and remains within a specified error band. This definition encompasses the major components which com- prise settling time. They include (1) propagation delay through the amplifier; (2) slewing time to approach the final output value; (3) the time of recovery from the overload associated with slewing and (4) linear settling to within the specified error band. Figure 19a. Inverting Amplifier Configuration (DIP Pinout) Figure 20a. Unity-Gain Buffer Amplifier Configuration (DIP Pinout) Figure 19b. Inverter Large Signal Pulse Response Figure 20b. Buffer Large Signal Pulse Response Figure 19c. Inverter Small Signal Pulse Response Figure 20c. Buffer Small Signal Pulse Response OFFSET NULLING The input offset voltage of the AD841 is very low for a high speed op amp, but if additional nulling is required, the circuit shown in Figure 21 can be used. Figure 21. Offset Nulling (DIP Pinout) |
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