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AD8321AR-REEL Scheda tecnica(PDF) 9 Page - Analog Devices |
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AD8321AR-REEL Scheda tecnica(HTML) 9 Page - Analog Devices |
9 / 19 page AD8321 –9– REV. 0 Basic Connection Figure 25 shows the basic schematic for operating the AD8321 in single-ended inverting mode. To operate in inverting mode, connect the input signal through an ac coupling capacitor to VIN–; VIN+ should be decoupled to ground with a 0.1 µF capacitor. Because the amplifier operates from a single supply, and the differential input pins are biased to approximately VCC/2, the differential inputs must be ac-coupled using 0.1 µF capacitors. For operation in the noninverting mode, the VIN– pin should be decoupled to ground via a 0.1 µF capacitor, with the input signal being fed to the AD8321 through the (ac-coupled) VIN+ pin. Inverting mode should be chosen if the AD8321 is being used as a drop-in replacement for the AD8320 (the AD8321 predecessor). Balanced differential inputs to the AD8321 may also be applied at an amplitude that is one-half the specified single-ended input amplitude. See the Differential Inputs section for more on this mode of operation. Power Supply and Decoupling The AD8321 should be powered with a good quality (i.e., low noise) single supply of 9 V. Although the AD8321 circuit will function at voltages lower than 9 V, optimum performance will not be achieved at lower supply settings. Careful attention must be paid to decoupling the power supply pins. A 10 µF capacitor located in near proximity to the AD8321 is required to provide good decoupling for lower frequency signals. In addition, and more importantly, five 0.1 µF decoupling capacitors should be located close to each of the five power supply pins (7, 8, 9, 17 and 20). A 0.1 µF capacitor must also be connected to the pins labeled BYP1 and BYP2 (Pins 5 and 14) to provide decoupling to internal nodes of the device. All six ground pins should be connected to a common low impedance ground plane. Input Bias, Impedance and Termination On the input side, the VIN+ and VIN– have a dc bias level equal to (VCC/2)–0.2 V. The input signal must therefore be ac- coupled before being applied to either input pin. The input impedance, when operated in single-ended mode is roughly 820 Ω (900 Ω in differential mode). An external shunt resis- tance (R1) to ground of 82.5 Ω is required to create a single- ended input impedance of close to 75 Ω. If single-ended 50 Ω termination is required, a 53.6 Ω shunt resistor may be used. Differential input operation may be achieved by using a shunt resistor of 41 Ω to ground on each of the inputs, or 82.6 Ω across the inputs resulting in a differential input impedance of approximately 75 Ω. Note: to avoid dc loading of either the VIN+ or VIN– pin, the ac-coupling capacitor must be placed between the input pin(s) and the shunt resistor(s). Refer to the Differential Inputs section for more details on this mode of operation. Output Bias, Impedance and Termination On the output side, the VOUT pin is also dc-biased to VCC/2 or midway between the supply voltage and ground. The output signal must therefore be ac-coupled before being applied to the load. The dc-bias voltage is available on the BYP1 and BYP2 pins (Pins 5 and 14 respectively) and can be used in dc-biasing schemes. These nodes must be decoupled to ground using a 0.1 µF capacitor as shown in Figure 25. If the BYP1 and/or BYP2 voltages are used externally, they should be buffered. External back termination resistors are not required when using the AD8321. The output impedance of the AD8321 is 75 Ω and is maintained dynamically. This on chip back termination is maintained regardless of whether the amplifier is in forward transmit mode or reverse powered down mode. If the output signal is being evaluated on 50 Ω test equipment such as a spec- trum analyzer, a 75 Ω to 50 Ω adapter (commonly called a mini- mum loss pad) should be used to maintain a properly matched circuit. ATTENUATOR CORE DATA SHIFT REGISTER DATA LATCH AD8321 POWER- DOWN/ SWITCH INTER DATEN CLK VIN+ VIN– PD VOUT SDATA VCC VCC C8 0.1 F VCC C9 0.1 F VCC C10 0.1 F VCC C11 0.1 F BYP1 C5 0.1 F C2 0.1 F C1 0.1 F R1 82.5 INPUT DATEN CLK GND GND GND GND GND SDATA C4 0.1 F TO DIPLEXER RIN = 75 BYP2 VCC +9V Ce 0.1 F C6 10 F C7 0.1 F Figure 25. Basic Connection for Single-Ended Inverting Operation |
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