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AD8004AR-14-REEL7 Scheda tecnica(PDF) 11 Page - Analog Devices |
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AD8004AR-14-REEL7 Scheda tecnica(HTML) 11 Page - Analog Devices |
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11 / 16 page  REV. B AD8004 –11– FREQUENCY – MHz +2 –8 1 500 10 40 100 –2 0 –4 –6 VIN = 50mV 5VS RL = 100 –10 –12 –14 +2 –8 –2 0 –4 –6 –10 –12 –14 CL = 10pF CL = 0 CL = 10pF CL = 0 G = +2, RF = 1.10k G = –2, RF = 698 Figure 35. Frequency Response vs. Capacitive Loading, RL = 100 Ω Output FREQUENCY – MHz +2 –8 1 500 10 40 100 –2 0 –4 –6 –10 –12 –14 CL = 10pF CL = 0 G = +2 RL = 1k 5VS VIN = 50mV rms RF = 1.2k Figure 36. Flatness with 10 pF Capacitive Load DRIVING A SINGLE-SUPPLY A/D CONVERTER New CMOS A/D converters are placing greater demands on the amplifiers that drive them. Higher resolutions, faster conversion rates and input switching irregularities require superior settling characteristics. In addition, these devices run off a single +5 V supply and consume little power, so good single-supply operation with low power consumption are very important. The AD8004 is well positioned for driving this new class of A/D converters. Figure 37 shows a circuit that uses an AD8004 to drive an AD876, a single supply, 10-bit, 20 MSPS A/D converter that requires only 140 mW. Using the AD8004 for level shifting and driving, the A/D exhibits no degradation in performance com- pared to when it is driven from a signal generator. The analog input of the AD876 spans 2 V centered at about 2.6 V. The resistor network and bias voltages provide the level shifting and gain required to convert the 0 V to 1 V input signal to a 3.6 V to 1.6 V range that the AD876 wants to see. Biasing the noninverting input of the AD8004 at 1.6 V dc forces the inverting input to be at 1.6 V dc for linear operation of the amplifier. When the input is at 0 V, there is 3.2 mA flowing out of the summing junction via R1 (1.6 V/499 Ω). R3 has a current of 1.2 mA flowing into the summing junction (3.6 V–1.6 V)/ 1.65 k Ω. The difference of these two currents (2 mA) must flow through R2. This current flows toward the summing junction and requires that the output be 2 V higher than the summing junction or at 3.6 V. When the input is at 1 V, there is 1.2 mA flowing into the sum- ming junction through R3 and 1.2 mA flowing out through R1. These currents balance and leave no current to flow through R2. Thus the output is at the same potential as the inverting input or 1.6 V. The input of the AD876 has a series MOSFET switch that turns on and off at the sampling rate. This MOSFET is connected to a hold capacitor internal to the device. The on impedance of the MOSFET is about 50 Ω, while the hold capacitor is about 5 pF. In a worst case condition, the input voltage to the AD876 will change by a full-scale value (2 V) in one sampling cycle. When the input MOSFET turns on, the output of the op amp will be connected to the charged hold capacitor through the series resistance of the MOSFET. Without any other series resistance, the instantaneous current that flows would be 40 mA. This would cause settling problems for the op amp. The series 100 Ω resistor limits the current that flows instanta- neously after the MOSFET turns on to about 13 mA. This resistor cannot be made too large or the high frequency perfor- mance will be affected. The sampling MOSFET of the AD876 is closed for only half of each cycle or for 25 ns. Approximately seven time constants are required for settling to 10 bits. The series 100 Ω resistor along with the 50 Ω on resistance and the hold capacitor, create a 750 ps time constant. These values leave a comfortable margin for settling. Obtaining the same results with the op amp A/D combination as compared to driving with a signal generator indicates that the op amp is settling fast enough. Overall the AD8004 provides adequate buffering for the AD876 A/D converter without introducing distortion greater than that of the A/D converter by itself. 3.6V 1.6V +5V 10 F R2 1k R3 1.65k R1 499k 3.6V VIN 50 0.1 F 1.6V 1V 0V 100 +1.6V +3.6V REFT REFB 0.1 F 0.1 F 1/4 AD8004 AD876 Figure 37. AD8004 Driving the AD876 LAYOUT CONSIDERATIONS The specified high speed performance of the AD8004 requires careful attention to board layout and component selection. Table I shows the recommended component values for the AD8004 and Figures 39–41 show the layout for the AD8004 evaluation boards (14-lead DIP and SOIC). Proper RF design techniques and low parasitic component selection are mandatory. |
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