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AD7868BR Scheda tecnica(PDF) 10 Page - Analog Devices |
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AD7868BR Scheda tecnica(HTML) 10 Page - Analog Devices |
10 / 16 page AD7868 –10– REV. B AD7868 DAC LOW-PASS FILTER 16-BIT DIGITIZER MICRO- CONTROLLER Figure 11. AD7868 DAC Dynamic Performance Test Circuit The digitizer sampling is synchronized with the DAC update rate to ease FFT calculations. The digitizer samples the DAC output after the output has settled to its new value. Therefore, if the digitizer were to sample the output directly it would effec- tively be sampling a dc value each time. As a result, the dynamic performance of the DAC would not be measured correctly. Us- ing the digitizer directly on the DAC output would give better results than the actual performance of the DAC. Using a filter between the DAC and the digitizer means that the digitizer samples a continuously moving signal and the true dynamic per- formance of the AD7868 DAC output is measured. Figure 12 shows a typical 2048 point Fast Fourier Transform plot for the AD7868 DAC with an update rate of 83 kHz and an output frequency of 1 kHz. The SNR obtained from the graph is 73 dBs. Figure 12. AD7868 DAC FFT Plot Some applications will require improved performance versus fre- quency from the AD7868 DAC. In these applications, a simple sample-and-hold circuit such as that outlined in Figure 13 will extend the very good performance of the DAC to 20 kHz. Other applications will already have an inherent sample-and-hold function following the AD7868 DAC output. An example of this type of application is driving a switched-capacitor filter where the updating of the DAC is synchronized with the switched-capacitor filter. This inherent sample-and-hold function also extends the frequency range performance. Performance versus Frequency The typical performance plots of Figures 14 and 15 show the AD7868’s DAC performance over a wide range of input fre- quencies at an update rate of 83 kHz. The plot of Figure 14 is without a sample-and-hold on the DAC output while the plot of Figure 15 is generated with a sample-and-hold on the output. AD7868* LDAC VOUT Q ADG201HS S1 D1 IN1 AD711 *ADDITIONAL PINS OMITTED FOR CLARITY R2 2k2 C9 330pF 1µs ONE SHOT DELAY R1 2k2 LDAC Figure 13. DAC Sample-and-Hold Circuit TA = +25°C FREQUENCY – kHz 80 70 0 05 1 234 40 30 20 10 60 50 Figure 14. DAC Performance vs. Frequency (No Sample- and-Hold) TA = +25°C FREQUENCY – kHz 80 70 0 0 20 5 10 15 40 30 20 10 60 50 Figure 15. DAC Performance vs. Frequency (Sample-and- Hold) |
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