Motore di ricerca datesheet componenti elettronici
  Italian  ▼
ALLDATASHEETIT.COM

X  

AD7868AQ Scheda tecnica(PDF) 8 Page - Analog Devices

Il numero della parte AD7868AQ
Spiegazioni elettronici  LC2MOS Complete, 12-Bit Analog I/O System
Download  16 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

AD7868AQ Scheda tecnica(HTML) 8 Page - Analog Devices

Back Button AD7868AQ Datasheet HTML 4Page - Analog Devices AD7868AQ Datasheet HTML 5Page - Analog Devices AD7868AQ Datasheet HTML 6Page - Analog Devices AD7868AQ Datasheet HTML 7Page - Analog Devices AD7868AQ Datasheet HTML 8Page - Analog Devices AD7868AQ Datasheet HTML 9Page - Analog Devices AD7868AQ Datasheet HTML 10Page - Analog Devices AD7868AQ Datasheet HTML 11Page - Analog Devices AD7868AQ Datasheet HTML 12Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 8 / 16 page
background image
AD7868
–8–
REV. B
TIMING AND CONTROL
Communication with the AD7868 is managed by 6 dedicated
pins. These consist of separate serial clocks, word framing or
strobe pulses and data signals for both receiving and transmit-
ting data. Conversion starts and DAC updating are controlled
by two digital inputs; CONVST and LDAC. These inputs can
be asserted independently of the microprocessor by an external
timer when precise sampling intervals are required. Alterna-
tively, the LDAC and CONVST can be driven from a decoded
address bus allowing the microprocessor control over conversion
start and DAC updating as well as data communication to the
AD7868.
ADC Timing
Conversion control is provided by the CONVST input. A low to
high transition on CONVST input starts conversion and drives
the track/hold amplifier into its hold mode. Serial data then be-
comes available while conversion is in progress. The correspond-
ing timing diagram is shown in Figure 7. The word length is 16
bits; 4 leading zeros, followed by the 12-bit conversion result
starting with the MSB. The data is synchronized to the serial
clock output (RCLK) and is framed by the serial strobe (RFS).
Data is clocked out on a low to high transition of the serial clock
and is valid on the falling edge of this clock while the RFS out-
put is low. RFS goes low at the start of conversion and the first
serial data bit (which is the first leading zero) is valid on the first
falling edge of RCLK. All the ADC serial lines are open-drain
outputs and require external pull-up resistors.
The serial clock out is derived from the ADC master clock
source which may be internal or external. Normally, RCLK is
required during the serial transmission only. In these cases it can
be shut down (i.e., placed into high impedance) at the end of
conversion to allow multiple ADCs to share a common serial
bus. However, some serial systems (e.g., TMS32020) require a
serial clock which runs continuously. Both options are available
on the AD7868 ADC. With the CONTROL input at 0 V, RCLK
is noncontinuous and when it is at –5 V, RCLK is continuous.
DAC Timing
The AD7868 DAC contains two latches, an input latch and a
DAC latch. Data must be loaded to the input latch under the
control of the TCLK, TFS and DT serial logic inputs. Data is
then transferred from the input latch to the DAC latch under
the control of the LDAC signal. Only the data in the DAC latch
determines the analog output of the AD7868.
Data is loaded to the input latch under control of TCLK, TFS
and DT. The AD7868 DAC expects a 16-bit stream of serial
data on its DT input. Data must be valid on the falling edge of
TCLK. The TFS input provides the frame synchronization sig-
nal which tells the AD7868 DAC that valid serial data will be
available for the next 16 falling edges of TCLK. Figure 8 shows
the timing diagram for the serial data format.
Although 16 bits of data are clocked into the input latch, only
12 bits are transferred into the DAC latch. Therefore, 4 bits in
the stream are don’t cares since their value does not affect the
DAC latch data. The bit positions are 4 don’t cares followed by
the 12-bit DAC data starting with the MSB.
The LDAC signal controls the transfer of data to the DAC
latch. Normally, data is loaded to the DAC latch on the falling
edge of LDAC. However, if LDAC is held low, then serial data
is loaded to the DAC latch on the sixteenth falling edge of
TCLK. If LDAC goes low during the loading of serial data to
the input latch, no DAC latch update takes place on the falling
edge of LDAC. If LDAC stays low until the serial transfer is
completed, then the update takes place on the sixteenth falling
edge of TCLK. If LDAC returns high before the serial data
transfer is completed, no DAC latch update takes place.
NOTES
1EXTERNAL 4.7k
PULL-UP RESISTOR
2EXTERNAL 2k
PULL-UP RESISTOR
3CONTINUOUS RCLK (DASHED LINE) WHEN THE CONTROL INPUT = –5V AND
NONCONTINUOUS WHEN THE CONTROL INPUT = 0V
t13
t3
CONVST
RFS
1
RCLK
2, 3
DR
1
DB11
DB10
DB9
DB1
DB0
CONVERSION TIME
t1
t5
t2
t4
t6
Figure 7. ADC Control Timing Diagram
DB11
DB10
DB1
DB0
t7
t8
t9
t10
t11
TFS
TCLK
DT
DON'T
CARE
DON'T
CARE
DON'T
CARE
DON'T
CARE
Figure 8. DAC Control Timing Diagram


Codice articolo simile - AD7868AQ

Produttore elettroniciIl numero della parteScheda tecnicaSpiegazioni elettronici
logo
Analog Devices
AD7868 AD-AD7868_15 Datasheet
340Kb / 16P
   LC MOS Complete, 12-Bit Analog I/O System
REV. B
More results

Descrizione simile - AD7868AQ

Produttore elettroniciIl numero della parteScheda tecnicaSpiegazioni elettronici
logo
Analog Devices
AD7869 AD-AD7869 Datasheet
297Kb / 16P
   LC2MOS Complete, 14-Bit Analog I/O System
REV. A
AD7868 AD-AD7868_15 Datasheet
340Kb / 16P
   LC MOS Complete, 12-Bit Analog I/O System
REV. B
AD7869 AD-AD7869_15 Datasheet
224Kb / 16P
   LC MOS Complete, 14-Bit Analog I/O System
REV. B
AD7569JNZ AD-AD7569JNZ Datasheet
443Kb / 20P
   LC2MOS Complete, 8-Bit Analog I/0 Systems
REV. B
AD7569TQ AD-AD7569TQ Datasheet
443Kb / 20P
   LC2MOS Complete, 8-Bit Analog I/0 Systems
REV. B
AD7569 AD-AD7569 Datasheet
504Kb / 20P
   LC2MOS Complete, 8-Bit Analog I/0 Systems
REV. B
AD7569KNZ AD-AD7569KNZ Datasheet
506Kb / 20P
   LC2MOS Complete, 8-Bit Analog I/0 Systems
REV. B
AD7769 AD-AD7769 Datasheet
265Kb / 16P
   LC2MOS Analog I/O Port
REV. A
AD7847ANZ AD-AD7847ANZ Datasheet
494Kb / 12P
   LC2MOS Complete, Dual 12-Bit MDACS
REV. C
AD7837BRZ AD-AD7837BRZ Datasheet
494Kb / 12P
   LC2MOS Complete, Dual 12-Bit MDACs
REV. C
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16


Scheda tecnica Scarica

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEETIT.COM
Lei ha avuto il aiuto da alldatasheet?  [ DONATE ] 

Di alldatasheet   |   Richest di pubblicita   |   contatti   |   Privacy Policy   |   scambio Link   |   Ricerca produttore
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com