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AD7742YR Scheda tecnica(PDF) 8 Page - Analog Devices

Il numero della parte AD7742YR
Spiegazioni elettronici  Single and Multichannel, Synchronous Voltage-to-Frequency Converters
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

AD7742YR Scheda tecnica(HTML) 8 Page - Analog Devices

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REV. 0
AD7741/AD7742
–8–
As can be seen from Table II, the AD7741 has one input range
configuration whereas the AD7742 has unipolar/bipolar as
well as gain options depending on the status of the GAIN
and UNI/
BIP pins.
The transfer function for the AD7741 is shown in Figure 3.
Figure 4 shows the AD7742 transfer function for unipolar input
range configuration while the AD7742 transfer function for
bipolar input range configuration is shown in Figure 5.
OUTPUT
FREQUENCY
fOUT
fOUTMAX
(0.45 fCLKIN)
fOUTMIN
(0.05 fCLKIN)
0
INPUT
VOLTAGE VIN
REFIN
Figure 3. AD7741 Transfer Characteristic for Input Range
from 0 to VREF
OUTPUT
FREQUENCY
fOUT
fOUTMAX
(0.45 fCLKIN)
fOUTMIN
(0.05 fCLKIN)
0
VREF
GAIN
+
DIFFERENTIAL
INPUT VOLTAGE
Figure 4. AD7742 Transfer Characteristic for Unipolar
Differential Input Range: 0 V to VREF/Gain; the input
common-mode range must be between +0.5 V and
VDD – 1.75 V. UNI/BIP pin tied to VDD.
Table II. AD7741/AD7742 Input Range Selection
VIN(Min)
VIN(Max)
UNI/
BIP
GAIN
Gain, G
fOUT = 0.05 fCLKIN
fOUT = 0.45 fCLKIN
Part
N/A
N/A
X1
0
+VREF
AD7741
00X1
–VREF
+VREF
AD7742
01X2
–VREF/2
+VREF/2
AD7742
10X1
0
+VREF
AD7742
11X2
0
+VREF/2
AD7742
OUTPUT
FREQUENCY
fOUT
fOUTMAX
(0.45 fCLKIN)
fOUTMIN
(0.05 fCLKIN)
DIFFERENTIAL
INPUT VOLTAGE
VREF
GAIN
+
VREF
GAIN
Figure 5. AD7742 Transfer Characteristic for Bipolar
Differential Input Range: –VREF/Gain to +VREF/Gain; the
common-mode range must be between +0.5 V and
VDD – 1.75 V. UNI/BIP pin tied to GND.
VFC Modulator
The analog input signal to the AD7741/AD7742 is continu-
ously sampled by a switched capacitor modulator whose sam-
pling rate is set by a master clock input that may be supplied
externally or by a crystal-controlled on-chip clock oscillator.
However, the input signal is buffered on-chip before being ap-
plied to the sampling capacitor of the modulator. This isolates
the sampling capacitor charging currents from the analog input
pins.
This system is a negative feedback loop that tries to keep the net
charge on the integrator capacitor at zero, by balancing charge
injected by the input voltage with charge injected by the VREF.
The output of the comparator provides the digital input for the
1-bit DAC, so that the system functions as a negative feedback
loop that tries to minimize the difference signal (see Figure 6).
INTEGRATOR
COMPARATOR
+
CLK
1-BIT
STREAM
+
INPUT
+VREF
–VREF
Figure 6. AD7741/AD7742 Modulator Loop


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