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AD7484BST Scheda tecnica(PDF) 8 Page - Analog Devices |
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AD7484BST Scheda tecnica(HTML) 8 Page - Analog Devices |
8 / 12 page REV. PrC 7/13/01 PRELIMINARY TECHNICAL DATA AD7484 – 8 – 20 25 30 35 40 45 50 55 60 0 500 1000 1500 2000 2500 3000 THROUGHPUT - KSPS 1 µS 300 nS 700 nS POWER SAVING The AD7484 uses advanced design techniques to achieve very low power dissipation at high throughput rates. In addi- tion to this the AD7484 features two power saving modes, Nap Mode and Standby Mode. These modes are selected by bringing either the NAP or STBY pin to a logic high respec- tively. When operating the AD7484 in normal, fully powered mode, the current consumption is 18mA during conver- sion and the quiescent current is 5mA. Operating at a throughput rate of 1MSPS, the conversion time of 300nS contributes 27mW to the overall power dissipation. Figure 5. Normal Mode Power Dissipation Figure 6. NAP Mode Power Dissipation (400nS / 1µS) x (5V x 18mA) = 36mW While in NAP mode for the rest of the cycle, the AD7484 dissipates only 3mW of power. (600nS / 1µS) x (5V x 1mA) = 3mW Figure 5 below shows the AD7484 conversion sequence operating in normal mode. In NAP mode, all the internal circuitry except for the internal reference is powered down. In this mode, the power dissipation of the AD7484 is reduced to 5mW. When exiting NAP mode a minimum of 100nS must be waited before initiating a conversion. This is necessary to allow the internal circuitry to settle after power-up and for the track/hold to properly acquire the analog input signal. If the AD7484 is put into NAP mode after each conversion, the average power dissipation will be reduced but the throughput rate will be limited by the power-up time. Using the AD7484 with a throughput rate of 1MSPS while placing the part in NAP mode after each conversion would result in average power dissipation as follows: The power-up and conversion phase will contribute 36mW to the overall power dissipation. (300nS / 1µS) x (5V x 18mA) = 27mW For the remaining 700nS of the cycle, the AD7484 dissipates 17.5mW of power. (700nS / 1µS) x (5V x 5mA) = 17.5mW Thus the power dissipated during each cycle is: 27mW + 17.5mW = 44.5mW Thus the power dissipated during each cycle is: 36mW + 3mW = 39mW Figure 6 shows the AD7484 conversion sequence if putting the part into NAP mode after each conversion. 400nS 1 µS 600nS 100nS Figures 7 and 8 show a typical graphical representation of Power vs. Throughput for the AD7484 when in Normal and Nap modes respectively. 0 5 10 15 20 25 30 35 40 45 50 0 250 500 750 1000 1250 1500 1750 2000 THROUGHPUT - KSPS Figure 7. Normal Mode - Power vs. Throughput Figure 8. Nap Mode - Power vs. Throughput In STANDBY mode, all the internal circuitry is powered down and the power consumption of the AD7484 is re- duced to 5µW. The power-up time necessary before a conversion can be initiated is longer because the internal reference has been powered down. If using the internal reference of the AD7484, the ADC must be brought out of STANDBY mode 200µS before a conversion is initi- ated. Initiating a conversion before the required power-up time has elapsed will result in incorrect conversion data. If an external reference source is used and kept powered up while the AD7484 is in STANDBY mode, the power- up time required will be reduced. |
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