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AD670AD Scheda tecnica(PDF) 10 Page - Analog Devices |
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AD670AD Scheda tecnica(HTML) 10 Page - Analog Devices |
10 / 12 page AD670 REV. A –10– STRAIN GAGE MEASUREMENTS Many semiconductor-type strain gages, pressure transducers, and load cells may also be connected directly to the AD670. These types of transducers typically produce 30 mV full-scale per volt of excitation. In the circuit shown in Figure 15, the AD670 is connected directly to a Data Instruments model JP-20 load cell. The AD584 programmable voltage reference is used along with an AD741 op amp to provide the ±2.5 V excitation for the load cell. The output of the transducer will be ±150 mV for a force of ±20 pounds. The AD670 is configured for the ±128 millivolt range. The resolution is then approximately 2.1 ounces per LSB over a range of ±17 pounds. Scaling to exactly 2 ounces per LSB can be accomplished by trimming the refer- ence voltage which excites the load cell. Figure 15. AD670 Load Cell Interface MULTIPLEXED INPUTS Most data acquisition systems require the measurement of sev- eral analog signals. Multiple A/D converters are often used to digitize these inputs, requiring additional preamplification and buffer stages per channel. Since these signals vary slowly, a dif- ferential MUX can multiplex inputs from several transducers into a single AD670. And since the AD670’s signal-conditioning capability is preserved, the cost of several ADCs, differential amplifiers, and other support components can be reduced to that of a single AD670, a MUX, and a few digital logic gates. An AD7502 dual 4-channel MUX appears in Figure 16 multi- plexing four differential signals to the AD670. The AD7502’s decoded address is gated with the microprocessor’s write signal to provide a latching strobe at the flip-flops. A write cycle to the AD7502’s address then latches the two LSBs of the data word thereby selecting the input channel for subsequent conversions. Figure 16. Multiplexed Analog Inputs to AD670 SAMPLED INPUTS For those applications where the input signal is capable of slew- ing more than 1/2 LSB during the AD670’s 10 µs conversion cycle, the input should be held constant for the cycle’s duration. The circuit shown in Figure 17 uses a CMOS switch and two capacitors to sample/hold the input. The AD670’s STATUS output, once inverted, supplies the sample/hold (S/H) signal. A convert command applied on the CE, CS or R/W lines will initiate the conversion. The AD670’s STATUS output, once in- verted, supplies the sample/hold signal to the CD4066. The CD4066 CMOS switch shown in Figure 17 was chosen for its fast transition times, low on-resistance and low cost. The con- trol input’s propagation delay for switch-closed to switch-open should remain less than 150 ns to ensure that the sample-to- hold transition occurs before the first bit decision in the AD670. |
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