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AD671JD-750 Scheda tecnica(PDF) 4 Page - Analog Devices |
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AD671JD-750 Scheda tecnica(HTML) 4 Page - Analog Devices |
4 / 16 page AD671–SPECIFICATIONS DIGITAL SPECIFICATIONS (For all grades TMIN to TMAX, with VCC = +5 V 5%, VLOGIC = +5 V 10%, VEE = –5 V 5%, VREF = +5.000 V, unless otherwise noted) REV. B –4– Parameter Symbol Min Typ Max Units LOGIC INPUT High Level Input Voltage VIH +2.0 V Low Level Input Voltage VIL +0.8 V High Level Input Current (VIN = VLOGIC)IIH –10 +10 µA Low Level Input Current (VIN = 0 V) IIL –10 +10 µA Input Capacitance CIN 5pF LOGIC OUTPUTS High Level Output Voltage (IOH = 0.5 mA) VOH +2.4 V Low Level Output Voltage (IOL = 1.6 mA) VOL +0.4 V Output Capacitance COUT 5pF Specifications shown in boldface are tested on all devices at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested. Specifications subject to change without notice. SWITCHING SPECIFICATIONS Parameter Symbol Min Typ Max Units Conversion Time (AD671-500) tC 475 500 ns (AD671-750) tC 725 750 ns ENCODE Pulse Width High (AD671-500) tENC 20 30 ns (AD671-750) tENC 20 50 ns ENCODE Pulse Width Low tENCL 20 ns DAV Pulse Width (AD671-500) tDAV 75 200 ns (AD671-750) tDAV 75 300 ns ENCODE Falling Edge Delay tF 0ns Start New Conversion Delay tR 0ns Data and OTR Delay from DAV Falling Edge tDD 1 20 75 ns Data and OTR Valid before DAV Rising Edge tSS 2 20 75 ns NOTES 1t DD is measured from when the falling edge of DAV crosses 0.8 V to when the output crosses 0.4 V or 2.4 V with a 25 pF load capacitor on each output pin. 2t SS is measured from when the outputs cross 0.4 V or 2.4 V to when the rising edge of DAV crosses 2.4 V with a 25 pF load capacitor on each output pin. (For all grades TMIN to TMAX with VCC = +5 V 5%, VLOGIC = +5 V 10%, VEE = –5 V 5%, VIL = 0.8 V, VIH = 2.0 V, VOL = 0.4 V and VOH = 2.4 V) Figure 1. AD671 Timing Diagrams a. Encode Pulse HIGH b. Encode Pulse LOW |
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