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AD668S Scheda tecnica(PDF) 3 Page - Analog Devices |
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AD668S Scheda tecnica(HTML) 3 Page - Analog Devices |
3 / 16 page AD668J/A AD668K AD668S Parameter Min Typ Max Min Typ Max Min Typ Max Units AC CHARACTERISTICS Analog Settling Time (10% to 120% Step) to ±1% 60 * * ns to 1% of FSR to ±0.1% 90 * * ns to 0.1% of FSR to ±0.025% 120 * * ns to 0.025% of FSR Digital Settling Time Current to ±1% 30 * * ns to 1% of FSR to ±0.025% 90 * * ns to 0.025% of FSR Voltage (100 Ω Internal R L) 3 to 1% 50 * * ns to 1% of FSR to 0.1% 75 * * ns to 0.1% of FSR to 0.025% 110 * * ns to 0.025% of FSR Glitch Impulse 4 350 * * pV-sec Peak Amplitude 20 * * % of FSR Total Harmonic Distortion 5 –75 * * dB Multiplying Feedthrough Error 6 –62 * * dB FULL-SCALE TRANSITION 2 10% to 90% Rise Time 11 * * ns 90% to 10% Fall Time 11 * * ns POWER REQUIREMENTS +10.8 V to +16.5 V 27 32 ** mA –10.8 V to –16.5 V 7 9 * * –mA Power Dissipation 510 615 * * mW PSRR7 0.05 * * % of FSR/V TEMPERATURE RANGE Rated Specification 2 (J, K, S) 0 +70 * * –55 +125 °C Rated Specification (A) –40 +85 °C Storage –65 +150 * * * * °C NOTES *Same as AD668J/A. 1Measured in I OUT mode. Specified at nominal 5 V full-scale reference. 2Measured in V OUT mode, unless otherwise specified. Specified at nominal 5 V full-scale reference. 3Total resistance. Refer to Figure 4. 4At the major carry, driven by HCMOS logic. 5V OUT = 1 V p-p, VIN = 10% to 110%, 100 kHz. Digital Input All 1s. 6V IN = 200 mV p-p, 1 MHz Sine Wave. Digital Input all 0s. See Figure 20. 7Measured at 15 V ± 10% and 12 V ±10%. Specifications shown in boldface are tested on all producfion units at final elec- trical test. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* VCC to REFCOM . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +18 V VEE to REFCOM . . . . . . . . . . . . . . . . . . . . . . . . . .0 V to –18 V REFCOM to LCOM . . . . . . . . . . . . . . . . . . +100 mV to –10 V ACOM to LCOM . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mV THCOM to LCOM . . . . . . . . . . . . . . . . . . . . . . . . . . ±500 mV REFCOM to REFIN (1, 2) . . . . . . . . . . . . . . . . . . . . . . . . 18 V IBPO to LCOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 V IOUT to LCOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to VTH Digital Inputs to THCOM . . . . . . . . . . . . . –500 mV to +7.0 V REFIN1 to REFIN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 V VTH to THCOM . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +1.4 V Logic Threshold Control Input Current . . . . . . . . . . . . . 5 mA Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670 mW Storage Temperature Range Q (Cerdip) Package . . . . . . . . . . . . . . . . . . –65 °C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175 °C Thermal Resistance θ JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +75 °C/W θ JC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25°C/W *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AD668 REV. A –3– |
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