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CS5484-INZ Scheda tecnica(PDF) 4 Page - Cirrus Logic |
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CS5484-INZ Scheda tecnica(HTML) 4 Page - Cirrus Logic |
4 / 67 page CS5484 4 DS981F2 LIST OF FIGURES Figure 1. Oscillator Connections................................................................................................... 7 Figure 2. Multi-device UART Connections.................................................................................... 8 Figure 3. UART Serial Frame Format........................................................................................... 8 Figure 4. Active Energy Load Performance.................................................................................. 9 Figure 5. Reactive Energy Load Performance............................................................................ 10 Figure 6. IRMS Load Performance ............................................................................................. 10 Figure 7. SPI Data and Clock Timing ......................................................................................... 15 Figure 8. Multi-Device UART Timing .......................................................................................... 15 Figure 9. Signal Flow for V1, I1, P1, and Q1 Measurements ..................................................... 17 Figure 10. Signal Flow for V2, I2, P2, and Q2 Measurements ................................................... 17 Figure 11. Low-rate Calculations ................................................................................................18 Figure 12. Power-on Reset Timing ............................................................................................. 21 Figure 13. Zero-crossing Level and Zero-crossing Output on DOx ............................................ 22 Figure 14. Energy Pulse Generation and Digital Output Control ................................................ 23 Figure 15. Sag, Swell, and Overcurrent Detect .......................................................................... 24 Figure 16. Phase Sequence A, B, C for Rising Edge Transition ................................................ 25 Figure 17. Phase Sequence C, B, A for Rising Edge Transition ................................................ 26 Figure 18. Byte Sequence for Page Select................................................................................. 27 Figure 19. Byte Sequence for Register Read ............................................................................ 27 Figure 20. Byte Sequence for Register Write ............................................................................. 27 Figure 21. Byte Sequence for Instructions.................................................................................. 27 Figure 22. Byte Sequence for Checksum ................................................................................... 28 Figure 23. Calibration Data Flow ................................................................................................62 Figure 24. T Register vs. Force Temp ........................................................................................ 64 Figure 25. Typical Connection (Single-phase, 3-wire, 12S Electricity Meter)............................. 65 LIST OF TABLES Table 1. POR Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 2. Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 3. Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 |
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