AD6620AS datasheet(2/43 Pages) AD

Il numero della parte	AD6620AS

Spiegazioni elettronici	65 MSPS Digital Receive Signal Processor

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AD6620

–2–

REV. 0

I-RAM

256

20

C-RAM

256

20

Q-RAM

256

20

MRCF

RCF

MCICS

CIC5

SCALING

INTERLEAVE

DE-

INTERLEAVE

MULTI-

PLEXER

MCICS

CIC2

SCALING

MULTI-

PLEXER

EXP

SCALING

FREQUENCY

TRANSLATOR

3

18

I

Q

16

INPUT

DATA

3

EXP[2:0]

16

IN[15:0]

COMPLEX

NCO

fSAMP5

EXPLNV,

EXPOFF

TIMING

SYNC

I/O

CLK

A/B

RESET

SYNC RCF

SYNC CIC

SYNC NCO

PHASE

OFFSET

fSAMP2

fSAMP

MULTIPLEXER

SCALING, SOUT

SERIAL

PARALLEL

16

23

DVOUT

I/QOUT

A/BOUT

PARALLEL

OUTPUTS

AND

SERIAL I/O

16

OUT[15:0]

SCLK

SDI

SDO

SDFS

SDFE

SBM

WL[1:0]

AD

SDIV[3:0]

RCF COEFFICIENTS

NUMBER OF TAPS

DECIMATE FACTOR

ADDRESS OFFSET

CIC2, CIC5

DECIMATE FACTORS

SCALE FACTORS

NCO FREQUENCY

PHASE OFFSET

DITHER

SYNC MASK

INPUT MODE

REAL, DUAL, COMPLEX

FIXED OR WITH EXPONENT

SYNC M/S

OUTPUT

SCALE

FACTOR

JTAG

TRST

TCK

TMS

TDI

TDO

MICROPROCESSOR INTERFACE

DS

D[7:0] A[2:0]

R/W

DTACK

CS

MODE PAR/SER

CONTROL REGISTERS

MICROPORT AND

SERIAL ACCESS

(

W/R)

(RDY)

(

R/D)

OUTPUT

Figure 1. Block Diagram

TABLE OF CONTENTS

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1

ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

SPECIFICATIONS/TIMING . . . . . . . . . . . . . . . . . . . . . . . 4

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 11

EXPLANATION OF TEST LEVELS . . . . . . . . . . . . . . . . 11

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 12

PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . 13

INPUT DATA PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

OUTPUT DATA PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

FREQUENCY TRANSLATOR . . . . . . . . . . . . . . . . . . . . . 20

2ND ORDER CASCADED INTEGRATOR

COMB FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5TH ORDER CASCADED INTEGRATOR

COMB FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

RAM COEFFICIENT FILTER . . . . . . . . . . . . . . . . . . . . . 25

CONTROL REGISTERS AND ON-CHIP RAM . . . . . . . 27

PROGRAMMING THE AD6620 . . . . . . . . . . . . . . . . . . . 29

MICROPORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . 31

SERIAL PORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . 34

JTAG BOUNDARY SCAN . . . . . . . . . . . . . . . . . . . . . . . . 36

APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 43

ARCHITECTURE

As shown in Figure 1, the AD6620 has four main signal pro-

cessing stages: a Frequency Translator, two Cascaded Integrator

Comb FIR Filters (CIC2, CIC5), and a RAM Coefficient FIR

Filter (RCF). Multiple modes are supported for clocking data

into and out of the chip. Programming and control is accom-

plished via serial and microprocessor interfaces.

Input data to the chip may be real or complex. If the input data

is real, it may be clocked in as a single channel or interleaved

with a second channel. The two-channel input mode, called

Diversity Channel Real, is typically used in diversity receiver

applications. Input data is clocked in 16-bit parallel words,

IN[15:0]. This word may be combined with exponent input bits

EXP[2:0] when the AD6620 is being driven by floating-point or

gain-ranging analog-to-digital converters such as the AD6600.

Frequency translation is accomplished with a 32-bit complex

Numerically Controlled Oscillator (NCO). Real data entering

this stage is separated into in-phase (I) and quadrature (Q)

components. This stage translates the input signal from a digital

intermediate frequency (IF) to baseband. Phase and amplitude

dither may be enabled on-chip to improve spurious performance

of the NCO. A phase offset word is available to create a known

phase relationship between multiple AD6620s.

Following frequency translation is a fixed coefficient, high speed

decimating filter that reduces the sample rate by a program-

mable ratio between 2 and 16. This is a second order, cascaded

integrator comb FIR filter shown as CIC2 in Figure 1. (Note:

Decimation of 1 in CIC2 requires 2

× or greater clock into

AD6620). The data rate into this stage equals the input data

rate, fSAMP. The data rate out of CIC2, fSAMP2, is determined by

the decimation factor, MCIC2.

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