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AD640BE Scheda tecnica(PDF) 7 Page - Analog Devices |
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AD640BE Scheda tecnica(HTML) 7 Page - Analog Devices |
7 / 16 page AD640 REV. C –7– CIRCUIT DESCRIPTION The AD640 uses five cascaded limiting amplifiers to approxi- mate a logarithmic response to an input signal of wide dynamic range and wide bandwidth. This type of logarithmic amplifier has traditionally been assembled from several small scale ICs and numerous external components. The performance of these semidiscrete circuits is often unsatisfactory. In particular, the logarithmic slope and intercept (see FUNDAMENTALS OF LOGARITHMIC CONVERSION) are usually not very stable in the presence of supply and temperature variations even after laborious and expensive individual calibration. The AD640 employs high precision analog circuit techniques to ensure sta- bility of scaling over wide variations in supply voltage and tem- perature. Laser trimming, using ac stimuli and operating conditions similar to those encountered in practice, provides fully calibrated logarithmic conversion. Each of the amplifier/limiter stages in the AD640 has a small signal voltage gain of 10 dB ( ×3.162) and a –3 dB bandwidth of 350 MHz. Fully differential direct coupling is used throughout. This eliminates the many interstage coupling capacitors usually required in ac applications, and simplifies low frequency signal processing, for example, in audio and sonar systems. The AD640 is intended for use in demodulating applications. Each stage incorporates a detector (a full wave transconductance rectifier) whose output current depends on the absolute value of its input voltage. Figure 16 is a simplified schematic of one stage of the AD640. All transistors in the basic cell operate at near zero collector to base voltage and low bias currents, resulting in low levels of ther- mally induced distortion. These arise when power shifts from one set of transistors to another during large input signals. Rapid recovery is essential when a small signal immediately follows a large one. This low power operation also contributes signifi- cantly to the excellent long-term calibration stability of the AD640. The complete AD640, shown in Figure 17, includes two bias regulators. One determines the small signal gain of the amplifier stages; the other determines the logarithmic slope. These bias regulators maintain a high degree of stability in the resulting function by compensating for potentially large uncertainties in transistor parameters, temperature and supply voltages. A third biasing block is used to accurately control the logarithmic intercept. By summing the signals at the output of the detectors, a good approximation to a logarithmic transfer function can be achieved. The lower the stage gain, the more accurate the approximation, but more stages are then needed to cover a given dynamic range. The choice of 10 dB results in a theoretical periodic Q3 Q4 Q5 Q6 Q7 Q8 1.09mA PTAT 1.09mA PTAT R2 85 565 A Q2 R1 85 Q1 Q9 LOG OUT 565 A Q10 LOG COM 2.18mA PTAT R4 75 R3 75 SIG OUT SIG IN COMMON –VS Figure 16. Simplified Schematic of a Single AD640 Stage deviation or ripple in the transfer function of ±0.15 dB from the ideal response when the input is either a dc voltage or a square wave. The slope of the transfer function is unaffected by the input waveform; however, the intercept and ripple are waveform dependent (see EFFECT OF WAVEFORM ON INTERCEPT). The input will usually be an amplitude modulated sinusoidal carrier. In these circumstances the output is a fluctuating current at twice the carrier frequency (because of the full wave detection) whose average value is extracted by an external low-pass filter, which recovers a logarithmic measure of the baseband signal. Circuit Operation With reference to Figure 16, the transconductance pair Q7, Q8 and load resistors R3 and R4 form a limiting amplifier having a small signal gain of 10 dB, set by the tail current of nominally 2.18 mA at 27 °C. This current is basically proportional to abso- lute temperature (PTAT) but includes additional current to compensate for finite beta and junction resistance. The limiting output voltage is ±180 mV at 27°C and is PTAT. Emitter fol- lowers Q1 and Q2 raise the input resistance of the stage, provide level shifting to introduce collector bias for the gain stage and detectors, reduce offset drift by forming a thermally balanced quad with Q7 and Q8 and generate the detector biasing across resistors R1 and R2. Transistors Q3 through Q6 form the full wave detector, whose output is buffered by the cascodes Q9 and Q10. For zero input Q3 and Q5 conduct only a small amount (a total of about 32 µA) of the 565 µA tail currents supplied to pairs Q3–Q4 and Q5–Q6. This “pedestal” current flows in output cascode Q9 to the LOG OUT node (Pin 14). When driven to the peak output of the preceding stage, Q3 or Q5 (depending on signal polarity) conducts lost of the tail current, and the output rises to 532 µA. The LOG OUT current has thus changed by 500 µA as the input has changed from zero to its maximum value. Since the detectors are spaced at 10 dB intervals, the output increases by ATN OUT AMPLIFIER/LIMITER FULL-WAVE DETECTOR ATN LO ATN COM SIG +IN SIG –IN ATN COM COM 27 30 270 ATN IN 1k RG1 RG0 RG2 –VS BL1 +VS LOG OUT LOG COM SIG +OUT SIG –OUT BL2 ITC 20 1 INTERCEPT POSITIONING BIAS 19 3 2 4 18 5 6 GAIN BIAS REGULATOR AMPLIFIER/LIMITER FULL-WAVE DETECTOR AMPLIFIER/LIMITER FULL-WAVE DETECTOR 10dB AMPLIFIER/LIMITER FULL-WAVE DETECTOR 10dB 10dB AMPLIFIER/LIMITER FULL-WAVE DETECTOR 17 16 14 13 1k 7 11 10 9 8 12 SLOPE BIAS REGULATOR 15 10dB 10dB Figure 17. Block Diagram of the Complete AD640 |
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