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AD534KCHIP Scheda tecnica(PDF) 2 Page - Analog Devices

Il numero della parte AD534KCHIP
Spiegazioni elettronici  Internally Trimmed Precision IC Multiplier
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
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AD534KCHIP Scheda tecnica(HTML) 2 Page - Analog Devices

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AD534–SPECIFICATIONS
Model
AD534J
AD534K
AD534L
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
MULTIPLIER PERFORMANCE
Transfer Function
( X1 – X2 )(Y1 – Y2 )
10 V
+ Z
2
( X1 – X2 )(Y1 – Y2 )
10 V
+ Z
2
( X1 – X2 )(Y1 – Y2 )
10 V
+ Z
2
Total Error
1 (–10 V
≤ X, Y ≤ +10 V)
1.0
0.5
0.25
%
TA = min to max
±1.5
± 1.0
± 0.5
%
Total Error vs. Temperature
±0.022
± 0.015
± 0.008
%/
°C
Scale Factor Error
(SF = 10.000 V Nominal)
2
±0.25
± 0.1
± 0.1
%
Temperature-Coefficient of
Scaling Voltage
±0.02
± 0.01
± 0.005
%/
°C
Supply Rejection (
± 15 V ± 1V)
±0.01
± 0.01
± 0.01
%
Nonlinearity, X (X = 20 V p-p, Y = 10 V)
±0.4
± 0.2
0.3
± 0.10
0.12
%
Nonlinearity, Y (Y = 20 V p-p, X = 10 V)
±0.2
± 0.1
0.1
± 0.005
0.1
%
Feedthrough
3, X (Y Nulled,
X = 20 V p-p 50 Hz)
±0.3
± 0.15
0.3
± 0.05
0.12
%
Feedthrough
3, Y (X Nulled,
Y = 20 V p-p 50 Hz)
±0.01
± 0.01
0.1
± 0.003
0.1
%
Output Offset Voltage
±5
30
± 2
15
± 2
10
mV
Output Offset Voltage Drift
200
100
100
µV/°C
DYNAMICS
Small Signal BW (VOUT = 0.1 rms)
1
1
1
MHz
1% Amplitude Error (CLOAD = 1000 pF)
50
50
50
kHz
Slew Rate (VOUT 20 p-p)
20
20
20
V/
µs
Settling Time (to 1%,
∆V
OUT = 20 V)
2
2
2
µs
NOISE
Noise Spectral-Density SF = 10 V
0.8
0.8
0.8
µV/√Hz
SF = 3 V
4
0.4
0.4
0.4
µV/√Hz
Wideband Noise f = 10 Hz to 5 MHz
1
1
1
mV/rms
Wideband Noise f = 10 Hz to 10 kHz
90
90
90
µV/rms
OUTPUT
Output Voltage Swing
11
11
11
V
Output Impedance (f
≤ 1 kHz)
0.1
0.1
0.1
Output Short Circuit Current
(RL = 0, TA = min to max)
30
30
30
mA
Amplifier Open Loop Gain (f = 50 Hz)
70
70
70
dB
INPUT AMPLIFIERS (X, Y and Z)5
Signal Voltage Range (Diff. or CM
±10
± 10
± 10
V
Operating Diff.)
±12
± 12
± 12
V
Offset Voltage X, Y
±5
20
± 2
10
± 2
10
mV
Offset Voltage Drift X, Y
100
50
50
µV/°C
Offset Voltage Z
±5
30
± 2
15
± 2
±10
mV
Offset Voltage Drift Z
200
100
100
µV/°C
CMRR
60
80
70
90
70
90
dB
Bias Current
0.8
2.0
0.8
2.0
0.8
2.0
µA
Offset Current
0.1
0.1
0.05
0.2
µA
Differential Resistance
10
10
10
M
DIVIDER PERFORMANCE
Transfer Function (X1 > X2)
10 V
( Z2 − Z1)
( X1 − X2 )
+Y
1
10 V
( Z2 − Z1)
( X1 − X2 )
+Y
1
10 V
( Z2 − Z1)
( X1 − X2 )
+Y
1
Total Error
1 (X = 10 V, –10 V
≤ Z ≤ +10 V)
±0.75
± 0.35
± 0.2
%
(X = 1 V, –1 V
≤ Z ≤ +1 V)
±2.0
± 1.0
± 0.8
%
(0.1 V
≤ X ≤ 10 V, –10 V ≤ Z ≤ 10 V)
±2.5
± 1.0
± 0.8
%
SQUARE PERFORMANCE
Transfer Function
( X1 − X2 )
2
10 V
+ Z
2
( X1 − X2 )
2
10 V
+ Z
2
( X1 − X2 )
2
10 V
+ Z
2
Total Error (–10 V
≤ X ≤ 10 V)
±0.6
± 0.3
± 0.2
%
SQUARE-ROOTER PERFORMANCE
Transfer Function (Z1
≤ Z
2)
10 V ( Z2 − Z1) + X2
10 V ( Z2 − Z1) + X2
10 V ( Z2 − Z1) + X2
Total Error
1 (1 V
≤ Z ≤ 10 V)
±1.0
± 0.5
± 0.25
%
POWER SUPPLY SPECIFICATIONS
Supply Voltage
Rated Performance
±15
± 15
± 15
V
Operating
±8
18
± 8
18
± 8
18
V
Supply Current
Quiescent
4
6
4
6
4
6
mA
PACKAGE OPTIONS
TO-100 (H-10A)
AD534JH
AD534KH
AD534LH
TO-116 (D-14)
AD534JD
AD534KD
AD534LD
Chips
AD534K Chips
(@ TA = + 25 C,
VS = 15 V, R
≥ 2k )
NOTES
1Figures given are percent of full scale,
± 10 V (i.e., 0.01% = 1 mV).
2May be reduced down to 3 V using external resistor between –V
S and SF.
3Irreducible component due to nonlinearity: excludes effect of offsets.
4Using external resistor adjusted to give SF = 3 V.
5See Functional Block Diagram for definition of sections.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final electrical
test. Results from those tests are used to calculate outgoing quality levels. All min and
max specifications are guaranteed, although only those shown in boldface are tested
on all production units.
REV. B
–2–


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