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otherwise under any patent or patent rights of Analog Devices.

a

AD5303/AD5313/AD5323*

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 1999

+2.5 V to +5.5 V, 230 A, Dual Rail-to-Rail

Voltage Output 8-/10-/12-Bit DACs

FUNCTIONAL BLOCK DIAGRAM

BUFFER

POWER-DOWN

LOGIC

RESISTOR

NETWORK

STRING

DAC

AD5303/AD5313/AD5323

DAC

REGISTER

DAC

REGISTER

>

SYNC

SCLK

DIN

GND

BUF A

SDO

CLR

BUF B

STRING

DAC

DCEN

LDAC

POWER-ON

RESET

PD

BUFFER

GAIN-SELECT

LOGIC

RESISTOR

NETWORK

INPUT

REGISTER

INPUT

REGISTER

INTERFACE

LOGIC

FEATURES

AD5303: Two Buffered 8-Bit DACs in One Package

AD5313: Two Buffered 10-Bit DACs in One Package

AD5323: Two Buffered 12-Bit DACs in One Package

16-Lead TSSOP Package

Micropower Operation: 300

A @ 5 V (Including

Reference Current)

Power-Down to 200 nA @ 5 V, 50 nA @ 3 V

+2.5 V to +5.5 V Power Supply

Double-Buffered Input Logic

Guaranteed Monotonic By Design Over All Codes

Buffered/Unbuffered Reference Input Options

Power-On-Reset to Zero Volts

SDO Daisy-Chaining Option

Simultaneous Update of DAC Outputs via LDAC Pin

Asynchronous CLR Facility

Low Power Serial Interface with Schmitt-Triggered

Inputs

On-Chip Rail-to-Rail Output Buffer Amplifiers

APPLICATIONS

Portable Battery Powered Instruments

Digital Gain and Offset Adjustment

Programmable Voltage and Current Sources

Programmable Attenuators

GENERAL DESCRIPTION

The AD5303/AD5313/AD5323 are dual 8-, 10- and 12-bit

buffered voltage output DACs in a 16-lead TSSOP package that

operate from a single +2.5 V to +5.5 V supply consuming 230

µA

at 3 V. Their on-chip output amplifiers allow the outputs to

swing rail-to-rail with a slew rate of 0.7 V/

µs. The AD5303/

AD5313/AD5323 utilize a versatile 3-wire serial interface that

operates at clock rates up to 30 MHz and is compatible with

standard SPI™, QSPI, MICROWIRE™ and DSP interface

standards.

The references for the two DACs are derived from two reference

pins (one per DAC). These reference inputs may be configured

as buffered or unbuffered inputs. The parts incorporate a power-

on-reset circuit that ensures that the DAC outputs power-up to

0 V and remain there until a valid write to the device takes place.

There is also an asynchronous active low CLR pin that clears

both DACs to 0 V. The outputs of both DACs may be updated

simultaneously using the asynchronous LDAC input. The

parts contain a power-down feature that reduces the current

consumption of the devices to 200 nA at 5 V (50 nA at 3 V) and

provides software-selectable output loads while in power-down

mode. The parts may also be used in daisy-chaining applications

using the SDO pin.

The low power consumption of these parts in normal operation

make them ideally suited to portable battery operated equip-

ment. The power consumption is 1.5 mW at 5 V, 0.7 mW at

3 V, reducing to 1

µW in power-down mode.

*Protected by U.S. Patent No. 5684481; other patents pending.

SPI is a trademark of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corporation.